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ADV7184
SD_OFF_Cb[7:0] SD Offset Cb Channel,
Address 0xE1 [7:0]
This register allows the user to select an offset for data on the
Cb channel only and adjust the hue of the picture. There is a
functional overlap with the HUE [7:0] register.
Table 31.SD_OFF_Cb Function
SD_OFF_Cb[7:0]
Description
0x80 (default)
0 mV offset applied to the Cb channel
0x00
568 mV offset applied to the Cb channel
0xFF
+568 mV offset applied to the Cb channel
SD_OFF_Cr [7:0] SD Offset Cr Channel, Address 0xE2 [7:0]
This register allows the user to select an offset for data on the
Cr channel only and adjust the hue of the picture. There is a
functional overlap with the HUE [7:0] register.
Table 32. SD_OFF_Cr Function
SD_OFF_Cr[7:0]
Description
0x80 (default)
0 mV offset applied to the Cr channel
0x00
568 mV offset applied to the Cr channel
0xFF
+568 mV offset applied to the Cr channel
BRI[7:0] Brightness Adjust, Address 0x0A [7:0]
This register controls the brightness of the video signal. It
allows the user to adjust the brightness of the picture.
Table 33. BRI Function
BRI[7:0]
Description
0x00 (default)
Offset of the luma channel = 0 mV
0x7F
Offset of the luma channel = +204 mV
0x80
Offset of the luma channel = 204 mV
HUE[7:0] Hue Adjust, Address 0x0B [7:0]
This register contains the value for the color hue adjustment. It
allows the user to adjust the hue of the picture.
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HUE[7:0] has a range of ±90°, with 0x00 equivalent to an
adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°.
The hue adjustment value is fed into the AM color demodulation
block. Therefore, it only applies to video signals that contain
chroma information in the form of an AM modulated carrier
(CVBS or Y/C in PAL or NTSC). It does not affect SECAM and
does not work on component video inputs (YPrPb).
Table 34. HUE Function
HUE[7:0]
Description
0x00 (default)
Phase of the chroma signal = 0°
0x7F
Phase of the chroma signal = +90°
0x80
Phase of the chroma signal = 90°
DEF_Y[5:0] Default Value Y, Address 0x0C [7:2]
If the ADV7184 loses lock on the incoming video signal or if
there is no input signal, the DEF_Y[5:0] bits allow the user to
specify a default luma value to be output. The register is used
under the following conditions:
If DEF_VAL_AUTO_EN bit is set to high and the
ADV7184 loses lock to the input video signal. This is the
intended mode of operation (automatic mode).
The DEF_VAL_EN bit is set, regardless of the lock status of
the video decoder. This is a forced mode that may be useful
during configuration.
The DEF_Y[5:0] values define the 6 MSBs of the output video.
The remaining LSBs are padded with 0s. For example, in 8-bit
mode, the output is Y[7:0] = {DEF_Y[5:0], 0, 0}.
The value for Y is set by the DEF_Y[5:0] bits. A value of 0x0D
produces a blue color in conjunction with the DEF_C[7:0]
default setting.
Register 0x0C has a default value of 0x36.
DEF_C[7:0] Default Value C, Address 0x0D [7:0]
The DEF_C[7:0] register complements the DEF_Y[5:0] value. It
defines the 4 MSBs of Cr and Cb values to be output if
The DEF_VAL_AUTO_EN bit is set to high and the
ADV7184 can’t lock to the input video (automatic mode).
DEF_VAL_EN bit is set to high (forced output).
The data that is finally output from the ADV7184 for the
chroma side is Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0}, Cb[7:0] =
{DEF_C[3:0], 0, 0, 0, 0}.
The values for Cr and Cb are set by DEF_C[7:0] bits. A value of
0x7C produces a blue color in conjunction with the DEF_Y[5:0]
default setting.
DEF_VAL_EN Default Value Enable, Address 0x0C [0]
This bit forces the use of the default values for Y, Cr, and Cb.
Refer to the descriptions for DEF_Y and DEF_C for additional
information. In this mode, the decoder also outputs a stable
27 MHz clock, HS, and VS.
0 (default)—Outputs a colored screen determined by user-
programmable Y, Cr, and Cb values when the decoder free-
runs. Free-run mode is turned on and off by the
DEF_VAL_AUTO_EN bit.
1—Forces a colored screen output determined by user-
programmable Y, Cr, and Cb values. This overrides picture
data even if the decoder is locked.