參數(shù)資料
型號： ADV7184
廠商： Analog Devices, Inc.
英文描述： Multiformat SDTV Video Decoder with Fast Switch Overlay Support
中文描述： 標清多格式視頻解碼器支持快速開關(guān)重疊
文件頁數(shù)： 56/108頁
文件大?。?/td> 925K
代理商： ADV7184
ADV7184
Gemstar, PDC, VPS, or UTC
: The user can select between
triggering an interrupt request each time sliced data is available
or triggering an interrupt request only when the sliced data has
changed. Selection is made via the GS_VPS_PDC_UTC_CB_
CHANGE bit.
Rev. 0 | Page 56 of 108
The sequence for the interrupt-based reading of the VDP I
2
C
data registers is the following for the CCAP standard.
1.
User unmasks CCAP interrupt mask bit (0x50 Bit 0, User
Sub Map = 1). CCAP data occurs on the incoming video.
VDP slices CCAP data and places it in the VDP readback
registers.
The VDP CCAP available bit goes high and the VDP
module signals to the interrupt controller to stimulate an
interrupt request (for CCAP in this case).
The user reads the interrupt status bits (User Sub Map) and
sees that new CCAP data is available (0x4E Bit 0, User Sub
Map = 1).
The user writes 1 to the CCAP interrupt clear bit (0x4F
Bit 0, User Sub Map = 1) in the Interrupt I
2
C space (this is
a self-clearing bit). This clears the interrupt on the INTRQ
pin but does NOT have an effect in the VDP I
2
C area.
The user reads the CCAP data from the VDP I
2
C area.
The user writes to a bit, CC_CLEAR in the VDP_STATUS
[0] register, (0x78 Bit 0, User Sub Map = 1) to signify the
CCAP data has been read (=> the VDP CCAP can be
updated at the next occurrence of CCAP).
Back to step 2.
Interrupt Mask Register Details
The following bits set the interrupt mask on the signal from the
VDP VBI data slicer.
2.
3.
4.
5.
6.
7.
VDP_CCAPD_MSKB Address 0x50 [0], User Sub Map
0 (default)—Disables interrupt on VDP_CCAPD_Q signal.
1—Enables interrupt on VDP_CCAPD_Q signal.
VDP_CGMS_WSS_CHNGD_MSKB Address 0x50 [2], User
Sub Map
0 (default)—Disables interrupt on VDP_CGMS_WSS_
CHNGD_Q signal.
1—Enables interrupt on VDP_CGMS_WSS_CHNGD_Q
signal.
VDP_GS_VPS_PDC_UTC_CHNG_MSKB Address 0x50 [4],
User Sub Map
0 (default)—Disables interrupt on
VDP_GS_VPS_PDC_UTC_CHNG_Q signal.
1—Enables interrupt on VDP_GS_VPS_PDC_UTC_CHNG_Q
signal.
VDP_VITC_MSKB Address 0x50 [6], User Sub Map
0 (default)—Disables interrupt on VDP_VITC_Q signal.
1—Enables interrupt on VDP_VITC_Q signal.
Interrupt Status Register Details
The following read-only bits contain data detection information
from the VDP module from the time the status bit has been last
cleared or unmasked.
VDP_CCAPD_Q Address 0x4E [0], User Sub Map
0 (default)—CCAP data has not been detected.
1—CCAP data has been detected.
VDP_CGMS_WSS_CHNGD_Q Address 0x4E [2], User Sub
Map
0 (default)—CGMS or WSS data has not been detected.
1—CGM or WSS data has been detected.
VDP_GS_VPS_PDC_UTC_CHNG_Q Address 0x4E [4], User
Sub Map
0 (default)—Gemstar, PDC, UTC, or VPS data has not been
detected.
1—Gemstar, PDC, UTC, or VPS data has been detected.
VDP_VITC_Q Address 0x4E [6], User Sub Map, read only
0 (default)—VITC data has not been detected.
1—VITC data has been detected.
Interrupt Status Clear Register Details
It is not necessary to write 0 to these write-only bits as they
automatically reset when they are set (self-clearing).
VDP_CCAPD_CLR Address 0x4F [0], User Sub Map
1—Clears VDP_CCAP_Q bit.
VDP_CGMS_WSS_CHNGD_CLR Address 0x4F [2], User
Sub Map
1—Clears VDP_CGMS_WSS_CHNGD_Q bit.
VDP_GS_VPS_PDC_UTC_CHNG_CLR Address 0x4F [4],
User Sub Map
1—Clears VDP_GS_VPS_PDC_UTC_CHNG_Q bit.
VDP_VITC_CLR Address 0x4F [6], User Sub Map
1—Clears VDP_VITC_Q bit.
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