參數(shù)資料
型號： ADV7184
廠商： Analog Devices, Inc.
英文描述： Multiformat SDTV Video Decoder with Fast Switch Overlay Support
中文描述： 標清多格式視頻解碼器支持快速開關重疊
文件頁數(shù)： 55/108頁
文件大小： 925K
代理商： ADV7184
ADV7184
I
2
C Interface
Dedicated I
2
C readback registers are available for CCAP,
CGMS, WSS, Gemstar, VPS, PDC/UTC and VITC. Because
teletext is a high data rate standard, data extraction is supported
only through the ancillary data packet. The details of these
registers and their access procedure are described next.
Rev. 0 | Page 55 of 108
User Interface for I
2
C Readback Registers
The VDP decodes all enabled VBI data standards in real time.
Since the I
2
C access speed is much lower than the decoded
rate, when the registers are being accessed they may be updated
with data from the next line. In order to avoid this, VDP has
a self-clearing CLEAR bit and an AVAILABLE status bit
accompanying all the I
2
C readback registers.
The user has to clear the I
2
C readback register by writing a high
to the CLEAR bit. This resets the state of the AVAILABLE bit to
low and indicates that the data in the associated readback
registers is not valid. After the VDP decodes the next line of the
corresponding VBI data, the decoded data is placed in the I
2
C
readback register and the AVAILABLE bit is set to HIGH to
indicate that valid data is now available.
Though the VDP decodes this VBI data in subsequent lines if
present, the decoded data is not updated to the readback
registers until the CLEAR bit is set high again. However, this
data is available through the 656 ancillary data packets.
The CLEAR and AVAILABLE bits are in the VDP_CLEAR
(0x78, User Sub Map, write only) and VDP_STATUS (0x78,
User Sub Map, read only) registers.
Example I
2
C Readback Procedure
The following tasks have to be performed to read one packet
(line) of PDC data from the decoder.
1.
Write 10 to I2C_GS_VPS_PDC_UTC[1:0] (0x9C, User Sub
Map) to specify that PDC data has to be updated to I
2
C
registers.
2.
Write high to the GS_PDC_VPS_UTC_CLEAR bit (0x78,
User Sub Map) to enable I
2
C register updating.
3.
Poll the GS_PDC_VPS_UTC_AVL bit (0x78, User Sub
Map) going high to check the availability of the PDC
packets.
4.
Read the data bytes from the PDC I
2
C registers. To read
another line or packet of data the above steps have to be
repeated.
To read a packet of CC, CGMS, or WSS data, steps 1 through 3
only are required since they have dedicated registers.
VDP—Content-Based Data Update
For certain standards like WSS, CGMS, Gemstar, PDC, UTC,
and VPS the information content in the signal transmitted
remains the same over numerous lines and the user may want to
be notified only when there is a change in the information
content or loss of the information content. The user must
enable content-based updating for the required standard
through the GS_VPS_PDC_UTC_CB_CHANGE and
WSS_CGMS_CB_CHANGE bits. Thus the AVAILABLE bit
shows the availability of that standard only when its content
changes.
Content-based updating also applies to loss of data at the lines
where some data was present before. Thus, for standards like
VPS, Gemstar, CGMS, and WSS, if no data arrives in the next
four lines programmed, the corresponding AVAILABLE bit in
the VDP_STATUS
register is set high and the content in the I
2
C
registers for that standard is set to zero. The user has to write
high to the corresponding CLEAR bit so that when a valid line
is decoded after some time, the decoded results are available
into the I
2
C registers, with the AVAILABLE status bit set high.
If content-based updating is enabled, the AVAILABLE bit is set
high (assuming the CLEAR bit was written) in the following cases:
The data contents change.
Data was being decoded and four lines with no data have
been detected.
No data was being decoded and new data is now being
decoded.
GS_VPS_PDC_UTC_CB_CHANGE Enable Content-Based
Updating for Gemstar/VPS/PDC/UTC, Address 0x9C [5],
User Sub Map
0—Disables content-based updating.
1 (default)—Enables content-based updating.
WSS_CGMS_CB_CHANGE Enable Content-Based Updating
for WSS/CGMS, Address 0x9C [4], User Sub Map
0—Disables content-based updating.
1 (default)—Enables content-based updating.
VDP—Interrupt-Based Reading of VDP I
2
C registers
Some VDP status bits are also linked to the interrupt request
controller so that the user does not have to poll the
AVAILABLE status bit. The user can configure the video
decoder to trigger an interrupt request on the INTRQ pin in
response to the valid data available in I
2
C registers. This
function is available for the following data types:
CGMS or WSS:
The user can select between triggering an
interrupt request each time sliced data is available or triggering
an interrupt request only when the sliced data has changed.
Selection is made via the WSS_CGMS_CB_CHANGE bit.
相關PDF資料
PDF描述
ADV7184BSTZ Multiformat SDTV Video Decoder with Fast Switch Overlay Support
ADV7188 Multiformat SDTV Video Decoder with Fast Switch Overlay Support
ADV7189B Multiformat SDTV Video Decoder
ADV7189BBSTZ268H Multiformat SDTV Video Decoder
ADV7189BKSTZ10F Multiformat SDTV Video Decoder
相關代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7184BSTZ 功能描述:IC DECODER VID SDTV MULTI 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799
ADV7185 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output
ADV7185KST 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output
ADV7186 制造商:AD 制造商全稱:Analog Devices 功能描述:Video Decoder and Display Processor
ADV7186BBCZ 功能描述:IC VIDEO DECODER 196CSPBGA RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*