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ADV7184
FSCLE Fsc Lock Enable, Address 0x51 [7]
The FSCLE bit allows the user to choose whether the status of
the color subcarrier loop is taken into account when the overall
lock status is determined and presented via Bits [1:0] in
STATUS_1. This bit must be set to 0 when operating in YPrPb
component mode to generate a reliable HLOCK status bit.
Rev. 0 | Page 25 of 108
0 (default)—Makes the overall lock status dependent on the
horizontal sync lock only.
1—Makes the overall lock status dependent on horizontal sync
lock and Fsc lock.
VS_Coast[1:0], Address 0xF9 [3:2]
These bits are used to set VS free-run (coast) frequency.
Table 25. VS_COAST[1:0] function
VS_COAST [1:0]
Description
00 (default)
Auto coast mode—follows VS
frequency from last video input
01
Forces 50 Hz coast mode
10
Forces 60 Hz coast mode
11
Reserved
CIL[2:0] Count Into Lock, Address 0x51 [2:0]
CIL[2:0] determines the number of consecutive lines for which
the into-lock condition must be true before the system switches
into the locked state, and reports this via STATUS_1[1:0]. It
counts the value in lines of video.
Table 26. CIL Function
CIL[2:0]
Description
000
1
001
2
010
5
011
10
100 (default)
100
101
500
110
1000
111
100000
COL[2:0] Count Out of Lock, Address 0x51 [5:3]
COL[2:0] determines the number of consecutive lines for which
the out of lock condition must be true before the system switches
into unlocked state, and reports this via STATUS_0[1:0]. It
counts the value in lines of video.
Table 27. COL Function
COL[2:0]
Description
000
1
001
2
010
5
011
10
100 (default)
100
101
500
110
1000
111
100000
ST_NOISE_VLD, HS Tip Noise Measurement Valid, Address
0xDE [3] (read only)
0—The ST_NOISE[10:0] measurement is not valid
1 (default)—The ST_NOISE[10:0] measurement is valid.
ST_NOISE[10:0] HS Tip Noise Measurement, Address 0xDE
[2:0], 0xDF [7:0]
The ST_NOISE[10:0] measures, over four fields, a readback
value of the average of the noise in the HSYNC tip.
ST_NOISE_VLD must be 1 for this measurement to be valid.
1 bit of ST_NOISE[10:0] = 1 ADC code.
1 bit of ST_NOISE[10:0] = 1.6 V/4096 = 390.625 μV.
COLOR CONTROLS
These registers allow the user to control the picture appearance,
including control of the active data in the event of video being
lost. These controls are independent of any other controls. For
instance, brightness control is independent of picture clamping,
although both controls affect the signal’s dc level.
CON[7:0] Contrast Adjust, Address 0x08 [7:0]
This register allows the user to adjust the contrast of the picture.
Table 28. CON Function
CON[7:0]
Description
0x80 (default)
Gain on luma channel = 1
0x00
Gain on luma channel = 0
0xFF
Gain on luma channel = 2
SD_SAT_Cb[7:0] SD Saturation Cb Channel,
Address 0xE3 [7:0]
This register allows the user to control the gain of the Cb
channel only. The user can adjust the saturation of the picture.
Table 29. SD_SAT_Cb Function
SD_SAT_Cb[7:0]
Description
0x80 (default)
Gain on Cb channel = 1
0x00
Gain on Cb channel = 0
0xFF
Gain on Cb channel = 2
SD_SAT_Cr[7:0] SD Saturation Cr Channel, Address 0xE4
[7:0]
This register allows the user to control the gain of the Cr channel
only. The user can adjust the saturation of the picture.
Table 30. SD_SAT_Cr Function
SD_SAT_Cr[7:0]
Description
0x80 (default)
Gain on Cr channel = 1
0x00
Gain on Cr channel = 0
0xFF
Gain on Cr channel = 2