參數(shù)資料
型號(hào)： ADV611JSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/46頁(yè)
文件大小： 0K
描述： IC CCTV DGTL VIDEO CODEC 120LQFP
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 視頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 8 b
三角積分調(diào)變： 無(wú)
電壓 - 電源，數(shù)字： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 120-LQFP
供應(yīng)商設(shè)備封裝： 120-LQFP（14x14）
包裝： 托盤(pán)
ADV611/ADV612
–17–
REV. 0
MIN Cr Value Register
Indirect (Read Only) Register Index 0x0B1
The MIN Cr Value register lets the host or DSP read the minimum pixel value for the Cr component in the unprocessed data. The
Host reads these values through the Host Interface.
[15:0]
Minimum Cr, MNCR[15:0]. 16-bit component pixel value (undefined at reset)
[31:0]
Reserved (always read zero)
MAX Cr Value Register
Indirect (Read Only) Register Index 0x0B2
The MAX Cr Value register lets the host or DSP read the maximum pixel value for the Cr component in the unprocessed data. The
Host reads these values through the Host Interface.
[15:0]
Maximum Cr, MXCR[15:0]. 16-bit component pixel value (undefined at reset)
[31:0]
Reserved (always read zero)
Compressed Field Size [HI]
Indirect (Read Only) Register Index 0x83
[15:0]
The DWORD Count registers hold the count of double (32-bit) words contained in the previously encoded field. This
count is useful for bit rate control algorithms that use a servo loop, which is locked to the expected number of double words
in the field. The registers are double buffered to ensure that the count remains constant while the next field's count accumu-
lates. Contains bits [19:4] of the DWORD count, reset is 0.
Compressed Field Size [LO]
Indirect (Read Only) Register Index 0xB4
[3:0]
Contains bits [3:0] of the DWORD count, reset is 0. For more information, see the DWORD Count 16 MSB Register
description.
Bin Width and Reciprocal Bin Width Registers
Indirect (Read/Write) Register Index 0x0100-0x0153
The RBW and BW values are calculated by the host or DSP from data in the Sum of Squares [0-41], Sum of Value, MIN Value, and
MAX Value registers; then are written to RBW and BW registers during encode mode to control the quantizer. The Host writes these
values through the Host Interface.
These registers contain a 16-bit interleaved table of alternating RBW/BW (RBW-even addresses and BW-odd addresses) values as
indexed on writes by address register. Bin Widths are 8.8, unsigned, 16-bit, fixed-point values. Reciprocal Bin Widths are 6.10, un-
signed, 16-bit, fixed-point values. Operation of this register is controlled by the host driver or the DSP (84 total entries) (undefined
at reset).
[15:0]
Bin Width Values, BW[15:0]
[15:0]
Reciprocal Bin Width Values, RBW[15:0]
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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