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參數(shù)資料
| 型號(hào)： | ADV611JSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCTV DGTL VIDEO CODEC 120LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻編解碼器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 8 b |
| 三角積分調(diào)變： | 無 |
| 電壓 - 電源，數(shù)字： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-LQFP（14x14） |
| 包裝： | 托盤 |
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ADV611/ADV612
–22–
REV. 0
Table IX. CCIR-656 Master and Slave Modes HSYNC, VSYNC, and FIELD Functionality
HSYNC, VSYNC and FIELD
Master Mode (HSYNC, VSYNC
Slave Mode (HSYNC, VSYNC
Functionality for CCIR-656
and FIELD Are Outputs)
and FIELD Are Inputs)
Encode Mode (video data is input
Pins are driven to reflect the states of the
These pins are used to control the
to the chip)
received time codes: EAV and SAV. This
blanking of video and sequencing (used
functionality is independent of the state of
with video decoders that do not con-
the 525-625 mode control. An encoder is
form to the correct number of samples
most likely to be in master mode.
per line [e.g., the Harris 8115]).
Decode Mode (video data is output
Pins are output to the precise timing definitions
Undefined—Use Master Mode
from the chip)
for CCIR-656 interfaces. The state of the pins
reflect the state of the EAV and SAV timing
codes that are generated in the output video data.
These definitions are different for 525 and 625 line
systems. The ADV611/ADV612 completely manages
the generation and timing of these pins.
Clocks and Strobes
All video data is synchronous to the video clock (VCLK).
The rising edge of VCLK is used to clock all data into the
ADV611/ADV612.
Synchronization and Blanking Pins
Three signals, which can be configured as inputs or outputs, are
used for video frame and field horizontal synchronization and
blanking. These signals are VSYNC, HSYNC, and FIELD.
VDATA Pins Functions With Differing Video Interface Formats
The functionality of the Video Interface pins depends on the
current video format.
Video Formats—CCIR-656
The ADV611/ADV612 supports a glueless video interface to
CCIR-656 devices when the Video Format is programmed to
CCIR-656 mode. CCIR-656 requires that 4:2:2 data (8 bits per
component) be multiplexed and transmitted over a single 8-bit
physical interface. A 27 MHz clock is transmitted along with the
data. This clock is synchronous with the data. The color space of
CCIR-656 is YCrCb.
When in master mode, the CCIR-656 mode does not require
any external synchronization or blanking signals to accompany
digital video. Instead, CCIR-656 includes special time codes
in the stream syntax that define horizontal blanking periods,
Table VIII. Component Digital Video Formats
Nominal
Bit/
Color
Data Rate
Master/
Format
Name
Component
Space
Sampling
(MHz)
Slave
I/F Width
Number
CCIR-656
8
YCrCb
4:2:2
27
Master
8
0x0
Multiplex Philips
8
YUV
4:2:2
27
Either
8
0x2
vertical blanking periods, and field synchronization (horizontal
and vertical synchronization information can be derived). These
time codes are called End-of-Active-Video (EAV) and Start-of-
Active-Video (SAV). Each line of video has one EAV and one
SAV time code. EAV and SAV have three bits of embedded
information to define HSYNC, VSYNC and Field information
as well as error detection and correction bits.
VCLK is driven with a 27 MHz, 50% duty cycle clock which is
synchronous with the video data. Video data is clocked on the
rising edge of the VCLK signal. When decoding, the VCLK
signal is typically transmitted along with video data in the
CCIR-656 physical interface.
Electrically, CCIR-656 specifies differential ECL levels to be
used for all interfaces. The ADV611/ADV612, however, only
supports unipolar, TTL logic thresholds. Systems designs that
interface to strictly conforming CCIR-656 devices (especially
when interfacing over long cable distances) must include ECL
level shifters and line drivers.
The functionality of HSYNC, VSYNC and FIELD Pins is
dependent on three programmable modes of the ADV611/
ADV612: Master-Slave Control, Encode-Decode Control and
525-625 Control. Table X summarizes the functionality of
these pins in various modes.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV611JSTZ | 制造商:Analog Devices 功能描述:IC VIDEO CODEC |
| ADV612 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Closed Circuit TV Digital Video Codec |
| ADV612BST | 制造商:Analog Devices 功能描述:Video Compression 120-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:INDUSTRIAL GRADE CCTV DIGITAL VID CODEC - Tape and Reel |
| ADV65056509 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV65909302 | 制造商:LG Corporation 功能描述:Frame Assembly |
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