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參數(shù)資料
| 型號(hào)： | ADV611JSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCTV DGTL VIDEO CODEC 120LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻編解碼器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 8 b |
| 三角積分調(diào)變： | 無 |
| 電壓 - 電源，數(shù)字： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-LQFP（14x14） |
| 包裝： | 托盤 |
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ADV611/ADV612
–15–
REV. 0
To vertically crop video while encoding, program the VSTART and VEND registers with actual video line numbers, which differ for each
field. The VSTART and VEND contents must be updated on each field, unless the quality box is enabled. Perform this updating as part of
the field-by-field BW register update process. To perform this dynamic update correctly, the update software must keep track of which
field is being processed next.
[9:0]
Vertical End, VEN[9:0]. 10-bit value defining the ending line of the active video region, with line numbers from 1-to-625
in PAL and 1-to-525 in NTSC. (0x3FF at reset—this value is larger than the max size of the largest video mode)
[15:10] Reserved (always write zero)
Compressed Field Size Limit
Indirect (Read/Write) Register Index 0x8
[15:0]
The DWORD Max Count 16 MSBs register selects the maximum number of double (32-bit) words for an encoded field.
When the value in the DWORD count registers reaches the DWORD Max Count, the Quantizer zeroes out all remaining
samples in the field. To enable the DWORD Max Counts operation, you must set (= 1) Bit 4 in Indirect register 0x7; all
other bits in Indirect register 0x7 are reserved ( = 0). Note that the 4 LSBs of the max count are 0000, so the max count is
selectable in 16-word increments. Contains bits [19:4] of the DWORD max count, reset to 0xffff
Mode Control #2
Indirect (Read/Write) Register Index 0x9
[2:0]
These bits control the contrast/attenuation of the area outside the quality box when the quality box is enabled. The
following settings control background contrast.
Setting
Contrast/Attenuation
000
Illegal
001
6 dB
010
12 dB
011
18 dB
100
24 dB
101
30 dB
[3]
Field Polarity Bit. This bit reverses the polarity of the FIELD pin. This bit operates as follows:
0
Normal Field Polarity (ADV601 Mode), reset value
1
Reverse Field Polarity. Polarity is opposite to the polarity in the FIELD pin timing diagrams.
[8:4]
Field Rate Reduction. To reduce this compressed data rate, the ADV601 can discard some video fields. Set field rate
reduction to zero to capture all fields, one to discard every other field, two to discard two fields out of three and so on.
Maximum possible field rate reduction send only one field out of 32.
[9]
Reserved, must set to 1. This bit must be set to take advantage of MERR detection logic. Resets to 0.
[10]
Reserved, resets to 1.
[11]
Ignore Field bit in decode, setting this bit eliminates black fields if field bits repeat from field to field in decode mode,
resets to 0.
Sum of Squares [0–41] Registers
Indirect (Read Only) Register Index 0x080 through 0x0A9
The Sum of Squares [0–41] registers hold values that correspond to the summation of squared values in corresponding Mallat blocks
[0–41]. These registers let the Host or DSP read sum of squares statistics from the ADV611/ADV612; using these values (with the
Sum of Value, MIN Value, and MAX Value) the host or DSP can then calculate the BW and RBW values. The ADV611/ADV612
indicates that the sum of squares statistics have been updated by setting (1) the STATR bit and asserting the STAT_R pin. Read the
statistics at any time. The Host reads these values through the Host Interface.
[15:0]
Sum of Squares, STS[15:0]. 16-bit values [0-41] for corresponding Mallat blocks [0-41] (undefined at reset). Sum of Square
values are 16-bit codes that represent the Most Significant Bits of values ranging from 40 bits for small blocks to 48 bits for
large blocks. The 16-bit codes have the following precision:
Blocks Precision
Sum of Squares Precision Description
0–2
48.–32
48.-bits wide, left shift code by 32-bits, and zero fill
3–11
46.–30
46.-bits wide, left shift code by 30-bits, and zero fill
12–20
44.–28
44.-bits wide, left shift code by 28-bits, and zero fill
21–29
42.–26
42.-bits wide, left shift code by 26-bits, and zero fill
30–41
40.–24
40.-bits wide, left shift code by 24-bits, and zero fill
If the Sum of Squares code were 0x0025 for block 10, the actual value would be 0x000940000000; if using that same
code, 0x0025, for block 30, the actual value would be 0x0025000000.
[31:0]
Reserved (always read zero)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV611JSTZ | 制造商:Analog Devices 功能描述:IC VIDEO CODEC |
| ADV612 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Closed Circuit TV Digital Video Codec |
| ADV612BST | 制造商:Analog Devices 功能描述:Video Compression 120-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:INDUSTRIAL GRADE CCTV DIGITAL VID CODEC - Tape and Reel |
| ADV65056509 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV65909302 | 制造商:LG Corporation 功能描述:Frame Assembly |
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