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參數(shù)資料
| 型號： | ADV611JSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/46頁 |
| 文件大小： | 0K |
| 描述： | IC CCTV DGTL VIDEO CODEC 120LQFP |
| 標準包裝： | 1 |
| 類型： | 視頻編解碼器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 8 b |
| 三角積分調(diào)變： | 無 |
| 電壓 - 電源，數(shù)字： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-LQFP（14x14） |
| 包裝： | 托盤 |
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ADV611/ADV612
–42–
REV. 0
Host Interface (Compressed Data) Register Timing
The diagrams in this section show transfer timing for host read and write transfers to the ADV611/ADV612’s Compressed Data
register. Accesses to the Compressed Data register are faster than access timing for the Indirect Address, Indirect Register Data, and
Interrupt Mask/Status registers. For information on access timing for the other registers, see the Host Interface (Indirect Address,
Indirect Register Data, and Interrupt Mask/Status) Register Timing section. Also note that as long as your system observes the RD
or WR signal assertion timing, your system does NOT have to wait for the ACK signal between new compressed data addresses.
Table XXVIII. Host (Compressed Data) Read Timing Parameters
Parameter
Description
Min
Max
Unit
tRD_CD_RDC
RD Signal, Compressed Data Direct Register, Read Cycle Time
28
N/A
ns
tRD_CD_PWA
RD Signal, Compressed Data Direct Register, Pulsewidth Asserted
10
N/A
ns
tRD_CD_PWD
RD Signal, Compressed Data Direct Register, Pulsewidth Deasserted
10
N/A
ns
tADR_CD_RDS
ADR Bus, Compressed Data Direct Register, Read Setup
2
N/A
ns
tADR_CD_RDH
ADR Bus, Compressed Data Direct Register, Read Hold (at 27 MHz VCLK)
2
N/A
ns
tDATA_CD_RDD
DATA Bus, Compressed Data Direct Register, Read Delay
N/A
10
ns
tDATA_CD_RDOH
DATA Bus, Compressed Data Direct Register, Read Output Hold
18
N/A
ns
tACK_CD_RDD
ACK Signal, Compressed Data Direct Register, Read Delay
N/A
18
ns
tACK_CD_RDOH
ACK Signal, Compressed Data Direct Register, Read Output Hold
9
N/A
ns
(I) ADR,
BE, CS
(I)
RD
(O) DATA
(O)
ACK
VALID
t
ADR CD RDS
t
DATA CD RDD
t
ACK CD RDD
t
ACK CD RDOH
t
DATA CD RDOH
t
ADR CD RDH
t
RD CD RDC
t
RD CD PWA
t
RD CD PWD
Figure 34. Host (Compressed Data) Read Transfer Timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV611JSTZ | 制造商:Analog Devices 功能描述:IC VIDEO CODEC |
| ADV612 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Closed Circuit TV Digital Video Codec |
| ADV612BST | 制造商:Analog Devices 功能描述:Video Compression 120-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:INDUSTRIAL GRADE CCTV DIGITAL VID CODEC - Tape and Reel |
| ADV65056509 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV65909302 | 制造商:LG Corporation 功能描述:Frame Assembly |
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