- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1901 > ADV611JSTZ (Analog Devices Inc)IC CCTV DGTL VIDEO CODEC 120LQFP PDF資料下載
參數(shù)資料
| 型號： | ADV611JSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCTV DGTL VIDEO CODEC 120LQFP |
| 標準包裝： | 1 |
| 類型： | 視頻編解碼器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 8 b |
| 三角積分調(diào)變： | 無 |
| 電壓 - 電源，數(shù)字： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應商設備封裝： | 120-LQFP（14x14） |
| 包裝： | 托盤 |
第1頁第2頁第3頁當前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
ADV611/ADV612
–12–
REV. 0
[5]
FIFO Stop, FIFOSTP. This condition indicates that the FIFO is full in decode mode and empty in encode mode. In
decode mode only, FIFOSTP status actually behaves more conservatively than this. In decode mode, even when FIFOSTP
is indicated, there are still 32 empty Dwords available in the FIFO and 32 more Dword writes can safely be performed.
This status bit indicates the following:
0
No FIFO Stop condition, reset value (FIFO_STP pin LO)
1
FIFO empty (encode) or full (decode) (FIFO_STP pin HI)
[6]
Memory Error, MERR. This condition indicates that an error has occurred at the DRAM memory interface. This condition can
be caused by a defective DRAM, the inability of the Host to keep up with the ADV611/ADV612 compressed data stream, or bit
errors in the data stream. Note that the ADV611/ADV612 recovers from this condition without host intervention.
0
No memory error condition, reset value
1
Memory error
[7]
Reserved (always read/write zero)
[8]
Interrupt Enable on CCIRER, IE_CCIRER. This mask bit selects the following:
0
Disable CCIR-656 data error interrupt, reset value
1
Enable interrupt on error in CCIR-656 data
[9]
Interrupt Enable on STATR, IE_STATR. This mask bit selects the following:
0
Disable Statistics Ready interrupt, reset value
1
Enable interrupt on Statistics Ready
[10]
Interrupt Enable on LCODE, IE_LCODE. This mask bit selects the following:
0
Disable Last Code Read interrupt, reset value
1
Enable interrupt on Last Code Read from FIFO
[11]
Interrupt Enable on FIFOSRQ, IE_FIFOSRQ. This mask bit selects the following:
0
Disable FIFO Service Request interrupt, reset value
1
Enable interrupt on FIFO Service Request
[12]
Interrupt Enable on FIFOERR, IE_FIFOERR. This mask bit selects the following:
0
Disable FIFO Stop interrupt, reset value
1
Enable interrupt on FIFO Stop
[13]
Interrupt Enable on FIFOSTP, IE_FIFOSTP. This mask bit selects the following:
0
Disable FIFO Error interrupt, reset value
1
Enable interrupt on FIFO Error
[14]
Interrupt Enable on MERR, IE_MERR. This mask bit selects the following:
0
Disable memory error interrupt, reset value
1
Enable interrupt on memory error
[15]
Reserved (always read/write zero)
Mode Control Register
Indirect (Read/Write) Register Index 0x00
This register holds configuration data for the ADV611/ADV612’s video interface format and controls several other video interface
features. For more information on formats and modes, see the Video Interface section. Bits in this register have the following functions:
[3:0]
Video Interface Format, VIF[3:0]. These bits select the interface format. Valid settings include the following (all
other values are reserved):
0x0
CCIR-656, reset value
0x2
MLTPX (Philips)
[4]
VCLK Output Divided by two, VCLK2. This bit controls the following:
0
Do not divide VCLK output (VCLKO = VCLK), reset value
1
Divide VCLK output by two (VCLKO = VCLK/2)
[5]
Video Interface Master/Slave Mode Select, M/S. This bit selects the following:
0
Slave mode video interface (External control of video timing, HSYNC-VSYNC-FIELD are inputs), reset value
1
Master mode video interface (ADV611/ADV612 controls video timing, HSYNC-VSYNC are outputs)
[6]
Video Interface 525/625 (NTSC/PAL) Mode Select, P/N. This bit selects the following:
0
525 mode video interface, reset value
1
625 mode video interface
相關PDF資料 |
PDF描述 |
|---|---|
| ADV7120KPZ30 | IC DAC VIDEO 3CH 30MHZ 44PLCC |
| ADV7125WBCPZ170 | IC DAC VIDEO 3-CH 330MHZ 48VFQFN |
| ADV7171KSZ-REEL | IC DAC VIDEO ENC NTSC 44-MQFP |
| ADV7172KSTZ-REEL | IC DAC VIDEO NTSC 6-CH 48-LQFP |
| ADV7177KSZ-REEL | IC DAC VIDEO NTSC 3-CH 44MQFP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADV611JSTZ | 制造商:Analog Devices 功能描述:IC VIDEO CODEC |
| ADV612 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Closed Circuit TV Digital Video Codec |
| ADV612BST | 制造商:Analog Devices 功能描述:Video Compression 120-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:INDUSTRIAL GRADE CCTV DIGITAL VID CODEC - Tape and Reel |
| ADV65056509 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV65909302 | 制造商:LG Corporation 功能描述:Frame Assembly |
發(fā)布緊急采購，3分鐘左右您將得到回復。