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參數(shù)資料
| 型號： | ADV611JSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCTV DGTL VIDEO CODEC 120LQFP |
| 標準包裝： | 1 |
| 類型： | 視頻編解碼器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 8 b |
| 三角積分調(diào)變： | 無 |
| 電壓 - 電源，數(shù)字： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-LQFP（14x14） |
| 包裝： | 托盤 |
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ADV611/ADV612
–18–
REV. 0
PIN FUNCTION DESCRIPTIONS
Clock Pins
Name
Pins
I/O
Description
VCLK/XTAL
2
I
A single clock (VCLK) or crystal input (across VCLK and XTAL). An acceptable
50% duty cycle clock signal is 27 MHz (CCIR-601 NTSC/PAL).
If using a clock crystal, use a parallel resonant, microprocessor grade clock crystal. If
using a clock input, use a TTL level input, 50% duty cycle clock with 1 ns (or less)
jitter (measured rising edge to rising edge). Slowly varying, low jitter clocks are
acceptable; up to 5% frequency variation in 0.5 sec.
VCLKO
1
O
VCLK Output or VCLK Output divided by two. Select function using Mode
Control register.
Video Interface Pins
Name
Pins
I/O
Description
VSYNC
1
I or O
Vertical Sync or Vertical Blank. This pin can be either an output (Master Mode) or
an input (Slave Mode). The pin operates as follows:
Output (Master) HI during inactive lines of video and LO otherwise
Input (Slave) a HI on this input indicates inactive lines of video
HSYNC
1
I or O
Horizontal Sync or Horizontal Blank. This pin can be either an output (Master
Mode) or an input (Slave Mode). The pin operates as follows:
Output (Master) HI during inactive portion of video line and LO otherwise
Input (Slave) a HI on this input indicates inactive portion of video line
Note that the polarity of this signal is modified using the Mode Control register. For
detailed timing information, see the Video Interface section.
FIELD
1
I or O
Field # or Frame Sync. Polarity of FIELD Pin can be reversed by setting Bit 3 in
Mode Control Register 2. The pin operates as follows:
Output (Master) HI during Field1 lines of video and LO otherwise
Input (Slave) a HI on this input indicates Field1 lines of video
ENC
1
O
Encode or Decode. This output pin indicates the coding mode of the ADV611/
ADV612 and operates as follows:
LO Decode Mode (Video Interface is output)
HI Encode Mode (Video Interface is input)
Note that this pin can be used to control bus enable pins for devices connected to
the ADV611/ADV612 Video Interface.
VDATA[7:0]
8
I/O
4:2:2 Video Data (8-bit digital component video data). These pins are inputs during
encode mode and outputs during decode mode. When outputs (decode) these pins
are compatible with 50 pF loads (rather than 30 pF as all other busses) to meet the
high performance and large number of typical loads on this bus.
The performance of these pins varies with the Video Interface Mode set in the
Mode Control register, see the Video Interface section of this data sheet for pin
assignments in each mode.
Note that the Mode Control register also sets whether the color component is
treated as either signed or unsigned.
STALL
1
I
Stall Mode. This pin stalls incoming video data driving encode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV611JSTZ | 制造商:Analog Devices 功能描述:IC VIDEO CODEC |
| ADV612 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Closed Circuit TV Digital Video Codec |
| ADV612BST | 制造商:Analog Devices 功能描述:Video Compression 120-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:INDUSTRIAL GRADE CCTV DIGITAL VID CODEC - Tape and Reel |
| ADV65056509 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV65909302 | 制造商:LG Corporation 功能描述:Frame Assembly |
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