參數(shù)資料
型號(hào): ADUC836BS
廠商: ANALOG DEVICES INC
元件分類: 微控制器/微處理器
英文描述: MicroConverter, Dual 16-Bit-ADCs with Embedded 62 kB Flash MCU
中文描述: 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52
封裝: 14 X 14 MM, MO-022-AC-1, MQFP-52
文件頁數(shù): 64/80頁
文件大?。?/td> 5913K
代理商: ADUC836BS
ADuC836
–64–
Power Supplies
The ADuC836’s operational power supply voltage range is 2.7 V
to 5.25 V. Although the guaranteed data sheet specifications are
given only for power supplies within 2.7 V to 3.6 V or +5% of the
nominal 5 V level, the chip will function equally well at any power
supply level between 2.7 V and 5.25 V.
Separate analog and digital power supply pins (AV
DD
and DV
DD
,
respectively) allow AV
DD
to be kept relatively free of noisy digital
signals that are often present on the system DV
DD
line. In this mode,
the part can also operate with split supplies, that is, using different
voltage supply levels for each supply. For example, this means that
the system can be designed to operate with a DV
DD
voltage level of
3 V while the AV
DD
level can be at 5 V, or vice-versa if required. A
typical split-supply configuration is shown in Figure 61.
DV
DD
48
34
20
ADuC836
5
6
AGND
AV
DD
+
0.1
F
10
F
ANALOG SUPPLY
10
F
DGND
35
21
47
0.1
F
DIGITAL SUPPLY
+
Figure 61. External Dual-Supply Connections
As an alternative to providing two separate power supplies, AV
DD
can be kept quiet by placing a small series resistor and/or ferrite
bead between it and DV
DD
, and then decoupling AV
DD
separately
to ground. An example of this configuration is shown in Figure 62.
In this configuration, other analog circuitry (such as op amps,
voltage reference, and so on) can be powered from the AV
DD
supply line as well.
DV
DD
48
34
20
ADuC836
5
6
AGND
AV
DD
0.1
F
10
F
DGND
35
21
47
0.1
F
+
DIGITAL SUPPLY
10
F
1.6
BEAD
Figure 62. External Single-Supply Connections
Notice that in Figures 61 and 62, a large value (10
F) reservoir
capacitor sits on DV
DD
and a separate 10
F capacitor sits on
AV
DD
. Also, local decoupling capacitors (0.1
F) are located at
each V
DD
pin of the chip. As per standard design practice, be sure
to include all of these capacitors and ensure the smaller capacitors
are closest to each V
DD
pin with lead lengths as short as possible.
Connect the ground terminal of each of these capacitors directly to
the underlying ground plane. Finally, it should also be noticed that,
at all times, the analog and digital ground pins on the ADuC836
should be referenced to the same system ground reference point.
Power-On Reset (POR) Operation
An internal POR (Power-On Reset) is implemented on the
ADuC836. For DV
DD
below 2.45 V, the internal POR will hold
the ADuC836 in reset. As DV
DD
rises above 2.45 V, an internal
timer will time out for typically 128 ms before the part is
released from reset. The user must ensure that the power supply
has reached a stable 2.7 V minimum level by this time. Likewise
on power-down, the internal POR will hold the ADuC836 in
reset until the power supply has dropped below 1 V. Figure 63
illustrates the operation of the internal POR in detail.
128ms TYP
1.0V TYP
128ms TYP
2.45V TYP
1.0V TYP
INTERNAL
CORE RESET
DV
DD
Figure 63. Internal Power-on-Reset Operation
Power Consumption
The DV
DD
power supply current consumption is specified in
normal, idle, and power-down modes. The AV
DD
power supply
current is specified with the analog peripherals disabled. The
normal mode power consumption represents the current drawn
from DV
DD
by the digital core. The other on-chip peripherals
(watchdog timer, power supply monitor, and so on) consume
negli
gible current and are therefore lumped in with the normal
operating current here. Of course, the user must add any cur
rents
sourced by the parallel and serial I/O pins, and those
sourced
by the DAC in order to determine the total current needed at the
ADuC836’s DV
DD
and AV
DD
supply pins. Also, current drawn
from the DV
DD
supply will increase by approximately 5 mA during
Flash/EE erase and program cycles.
REV. A
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