參數(shù)資料
型號: ADUC836BS
廠商: ANALOG DEVICES INC
元件分類: 微控制器/微處理器
英文描述: MicroConverter, Dual 16-Bit-ADCs with Embedded 62 kB Flash MCU
中文描述: 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52
封裝: 14 X 14 MM, MO-022-AC-1, MQFP-52
文件頁數(shù): 60/80頁
文件大?。?/td> 5913K
代理商: ADUC836BS
ADuC836
–60–
BAUD RATE GENERATION USING TIMER 3
The high integer dividers in a UART block means that high
speed baud rates are not always possible using some particular
crystals, e.g., using a 12 MHz crystal, a baud rate of 115200 is
not possible. To address this problem, the ADuC836 has added
a dedicated baud rate timer (Timer 3) specifically for generating
highly accurate baud rates.
Timer 3 can be used instead of Timer 1 or Timer 2 for generating
very accurate high speed UART baud rates including 115200 and
230400. Timer 3 also allows a much wider range of baud rates to
be obtained. In fact, every desired bit rate from 12 bits to 393216
bits can be generated to within an error of ±0.8%. Timer 3 also
frees up the other three timers allowing them to be used for dif-
ferent applications. A block diagram of Timer 3 is shown in
Figure 57.
(1 + T3FD/64)
2
T3 RX/TX
CLOCK
CORE
CLK
*
T3EN
RX
CLOCK
TX CLOCK
TIMER 1/TIMER 2
RX CLOCK (FIG 44)
FRACTIONAL
DIVIDER
0
0
1
1
TIMER 1/TIMER 2
TX CLOCK (FIG 44)
16
2
DIV
*
THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
Figure 57. Timer 3, UART Baud Rates
Two SFRs (T3CON and T3FD) are used to control Timer 3.
T3CON is the baud rate control SFR, allowing Timer 3 to be
used to set up the UART baud rate, and setting up the binary
divider (DIV).
Table XXXIII. T3CON SFR Bit Designations
Bit Name Description
7 T3EN Set to enable Timer 3 to generate the baud rate.
When set PCON.7, T2CON.4 and T2CON.5
are ignored. Cleared to let the baud rate be
generated as per a standard 8052.
6 ––– Reserved for Future Use
5 ––– Reserved for Future Use
4 ––– Reserved for Future Use
3 ––– Reserved for Future Use
2 DIV2 Binary Divider Factor
1 DIV1 DIV2 DIV1 DIV0 Bin Divider
0 DIV0 0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1
0
1
0
1
0
1
1
2
4
8
16
32
64
128
The appropriate value to write to the DIV2-1-0 bits can be cal-
culated using the following formula where
f
CORE
is the output of
the PLL, as described in the On-Chip PLL section. Note that the
DIV
value must be rounded down.
32
DIV
f
Baud Rate
( )
log
2
CORE
=
×
log
T3FD is the fractional divider ratio required to achieve the
required baud rate. We can calculate the appropriate value for
T3FD using the following formula. Note that the
T
3
FD
should
be rounded to the nearest integer.
T FD
3
f
Baud Rate
CORE
DIV
2
2
64
=
×
×
Once the values for
DIV
and
T3FD
are calculated, the actual
baud rate can be calculated using the following formula:
Actual Baud Rate
f
3
T FD
(
CORE
DIV
=
×
×
+
)
2
2
64
For a baud rate of 115200 while operating from the maximum
core frequency (CD = 0), we have:
=
(
=
×
(
.
3
2
12 582912
2
DIV
T FD
Dh
×
)
=
=
)
×
(
)
=
=
log
/log
.
.
12582912/
115200
2
1 77
1
115200
64
45 22
2
1
Therefore, the actual baud rate is 115439 bits.
Table XXXIV. Commonly Used Baud Rates Using Timer 3
Ideal %
Baud CD DIV T3CON T3FD Error
230400 0 0 80H 2DH 0.2
115200 0 1 81H 2DH 0.2
115200 1 0 80H 2DH 0.2
57600 0 2 82H 2DH 0.2
57600 1 1 81H 2DH 0.2
57600 2 0 80H 2DH 0.2
38400 0 3 83H 12H 0.1
38400 1 2 82H 12H 0.1
38400 2 1 81H 12H 0.1
38400 3 0 80H 12H 0.1
19200 0 4 84H 12H 0.1
19200 1 3 83H 12H 0.1
19200 2 2 82H 12H 0.1
19200 3 1 81H 12H 0.1
19200 4 0 80H 12H 0.1
9600 0 5 85H 12H 0.1
9600 1 4 84H 12H 0.1
9600 2 3 83H 12H 0.1
9600 3 2 82H 12H 0.1
9600 4 1 81H 12H 0.1
9600 5 0 80H 12H 0.1
38400 0 3 83H 12H 0.1
REV. A
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