參數(shù)資料
型號(hào)： ADUC836BS
廠商： ANALOG DEVICES INC
元件分類： 微控制器/微處理器
英文描述： MicroConverter, Dual 16-Bit-ADCs with Embedded 62 kB Flash MCU
中文描述： 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52
封裝： 14 X 14 MM, MO-022-AC-1, MQFP-52
文件頁(yè)數(shù)： 17/80頁(yè)
文件大小： 5913K
代理商： ADUC836BS
ADuC836
–17–
ADC SFR INTERFACE
Both ADCs are controlled and configured via a number of SFRs that are summarized here and described in more detail in the
following sections.
ADCSTAT ADC Status Register. Holds general status of the
primary and auxiliary ADCs.
ADCMODE ADC Mode Register. Controls general modes of
operation for primary and auxiliary ADCs
ADC0CON Primary ADC Control Register. Controls specific
configuration of primary ADC.
ADC1CON Auxiliary ADC Control Register. Controls
specific configuration of auxiliary ADC.
SF Sinc Filter Register. Configures the decimation
factor for the Sinc
3
filter and thus the primary
and auxiliary ADC update rates.
ICON Current Source Control Register. Allows the user
to control of the various on-chip current source
options.
ADC0M/H Primary ADC 16-bit conversion result is held in
these two 8-bit registers.
ADC1L/H
Auxiliary ADC 16-bit conversion result is held
in
these two 8-bit registers.
OF0M/H Primary ADC 16-bit Offset Calibration Coefficient
is held in these two 8-bit registers.
OF1L/H Auxiliary ADC 16-bit Offset Calibration Coefficient
is held in these two 8-bit registers.
GN0M/H Primary ADC 16-bit Gain Calibration
Coefficient
is held in these two 8-bit registers.
GN1L/H Auxiliary ADC 16-bit Gain Calibration Coefficient
is held in these two 8-bit registers.
ADCSTAT (ADC Status Register)
This SFR reflects the status of both ADCs including data ready, calibration, and various (ADC related) error and warning conditions
such as reference detect and conversion overflow/underflow flags.
SFR Address D8H
Power-On Default Value 00H
Bit Addressable Yes
Table IV. ADCSTAT SFR Bit Designations
Bit Name Description
7 RDY0 Ready Bit for Primary ADC.
Set by hardware on completion of ADC conversion or calibration cycle.
Cleared directly by the user or indirectly by writing to the mode bits to start another primary ADC conversion
or calibration. The primary ADC is inhibited from writing further results to its data or calibration registers
until the RDY0 bit is cleared.
6 RDY1 Ready Bit for Auxiliary ADC. Same definition as RDY0 referred to the auxiliary ADC.
5 CAL Calibration Status Bit.
Set by hardware on completion of calibration.
Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration.
4 NOXREF No External Reference Bit (only active if primary or auxiliary ADC is active)
.
Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below a specified threshold.
When set, conversion results are clamped to all ones, if using external reference.
Cleared to indicate valid V
REF
.
3 ERR0 Primary ADC Error Bit.
Set by hardware to indicate that the result written to the primary ADC data registers has been clamped to all
zeros or all ones. After a calibration, this bit also flags error conditions that caused the calibration registers not
to be written.
Cleared by a write to the mode bits to initiate a conversion or calibration.
2 ERR1 Auxiliary ADC Error Bit. Same definition as ERR0 referred to the auxiliary ADC.
1 ––– Reserved for Future Use
0 ––– Reserved for Future Use
REV. A
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