參數(shù)資料
型號(hào)： ADUC836BS
廠商： ANALOG DEVICES INC
元件分類： 微控制器/微處理器
英文描述： MicroConverter, Dual 16-Bit-ADCs with Embedded 62 kB Flash MCU
中文描述： 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52
封裝： 14 X 14 MM, MO-022-AC-1, MQFP-52
文件頁(yè)數(shù)： 50/80頁(yè)
文件大?。?/td> 5913K
代理商： ADUC836BS
ADuC836
–50–
P1.2 to P1.7
The remaining Port 1 pins (P1.2 to P1.7) can only be configured as
analog input (ADC) or digital input pins. By (power-on) default,
these pins are configured as analog inputs, i.e., 1 written in the
corresponding Port 1 register bit. To configure any of these pins
as digital inputs, the user should write a 0 to these port bits to
configure the corresponding pin as a high impedance digital input.
Figure 39 illustrates this function. Note that there are no output
drivers for Port 1 pins, and they therefore cannot be used as
outputs.
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
LATCH
Q
Q
P1.x
PIN
TO ADC
Figure 39. P1.2 to P1.7 Bit Latch and I/O Buffer
Port 2
Port 2 is a bidirectional port with internal pull-up resistors directly
controlled via the P2 SFR. Port 2 also emits the high order address
bytes during fetches from external program memory and middle
and high order address bytes during accesses to the 24-bit external
data memory space.
As shown in Figure 40, the output drivers of Port 2 are switchable
to an internal ADDR bus by an internal CONTROL signal for use
in external memory accesses (as for Port 0). In external memory
addressing mode (CONTROL = 1), the port pins feature push/
pull operation controlled by the internal address bus (ADDR line).
However, unlike the P0 SFR during external memory accesses,
the P2 SFR remains unchanged.
In general-purpose I/O port mode, Port 2 pins that have 1s written
to them are pulled high by the internal pull-ups (Figure 38), and in
that state can be used as inputs. As inputs, Port 2 pins being pulled
externally low will source current because of the internal pull-up
resistors. Port 2 pins with 0s written to them will drive a logic low
output voltage (V
OL
) and will be capable of sinking 1.6 mA.
ADDR
CONTROL
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
LATCH
Q
Q
DV
DD
P2.x
PIN
DV
DD
INTERNAL
PULL-UP
*
*
SEE FIGURE 38 FOR
DETAILS OF INTERNAL PULL-UP
Figure 40. Port 2 Bit Latch and I/O Buffer
Port 3
Port 3 is a bidirectional port with internal pull-ups directly controlled
via the P3 SFR.
Port 3 pins that have 1s written to them are pulled high by the
internal pull-ups, and in that state can be used as inputs. As inputs,
Port 3 pins being pulled externally low will source current because
of the internal pull-ups. Port 3 pins with 0s written to them will
drive a logic low output voltage (V
OL
) and will be capable of sink-
ing 1.6 mA.
Port 3 pins also have various secondary functions described in
Table XXV. The alternate functions of Port 3 pins can be activated
only if the corresponding bit latch in the P3 SFR contains a 1.
Otherwise, the port pin is stuck at 0.
Table XXV. Port 3, Alternate Pin Functions
Pin Alternate Function
P3.0 RxD (UART Input Pin)
(or Serial Data I/O in Mode 0)
P3.1 TxD (UART Output Pin)
(or Serial Clock Output in Mode 0)
P3.2
INT0
(External Interrupt 0)
P3.3
INT1
(External Interrupt 1)
P3.4 T0 (Timer/Counter 0 External Input)
PWMCLK (PWM External Clock)
P3.5 T1 (Timer/Counter 1 External Input)
P3.6
WR
(External Data Memory Write Strobe)
P3.7
RD
(External Data Memory Read Strobe)
Port 3 pins have the same bit latch and I/O buffer configurations
as the P1.0 and P1.1, as shown in Figure 41. The internal pull-up
configuration is also defined by the one in Figure 38.
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
LATCH
Q
Q
DV
DD
P3.x
PIN
INTERNAL
PULL-UP
*
*
SEE FIGURE 38
FOR DETAILS OF
INTERNAL PULL-UP
ALTERNATE
OUTPUT
FUNCTION
ALTERNATE
INPUT
FUNCTION
Figure 41. Port 3 Bit Latch and I/O Buffer
Additional Digital I/O
In addition to the port pins, the dedicated SPI/I2C pins (SCLOCK
and SDATA/MOSI) also feature both input and output functions.
Their equivalent I/O architectures are illustrated in Figure 42 and
Figure 44, respectively, for SPI operation, and in Figure 43 and
Figure 45 for I
2
C operation.
Notice that in I
2
C mode (SPE = 0), the strong pull-up FET (Q1) is
disabled leaving only a weak pull-up (Q2) present. By contrast, in
SPI mode (SPE = 1), the strong pull-up FET (Q1) is controlled
directly by SPI hardware, giving the pin push/pull capability.
In I
2
C mode (SPE = 0), two pull-down FETs (Q3 and Q4)
operate in parallel in order to provide an extra 60% or 70% of
current sinking capability. In SPI mode, however, (SPE = 1), only
one of the pull-down FETs (Q3) operates on each pin resulting
in sink capabilities identical to that of Port 0 and Port 2 pins.
On the input path of SCLOCK, notice that a Schmitt trigger
conditions the signal going to the SPI hardware to prevent false
triggers (double triggers) on slow incoming edges. For incoming
signals from the SCLOCK and SDATA pins going to I
2
C hardware,
a filter conditions the signals to reject glitches of up to 50 ns in
duration.
REV. A
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