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參數(shù)資料
| 型號： | ADT7463ARQZ-REEL |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 43/50頁 |
| 文件大小： | 726K |
| 描述： | IC REMOTE THERMAL CTRLR 24-QSOP |
| 產(chǎn)品變化通告： | MFG CHG Notification ADI to ON Semi QSOP 24ld Pkg (MSL) Change 17/Jun/2010 |
| 標準包裝： | 2,500 |
| 系列： | dBCool® |
| 功能： | 風扇控制，溫度監(jiān)控器 |
| 傳感器類型： | 內(nèi)部和外部 |
| 感應溫度： | -40°C ~ 120°C，外部傳感器 |
| 精確度： | ±1.5°C（最小值） |
| 拓撲： | ADC，比較器，風扇速度計數(shù)器，多路復用器，寄存器庫 |
| 輸出類型： | SMBus? |
| 輸出警報： | 無 |
| 輸出風扇： | 是 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 120°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 24-QSOP |
| 包裝： | 帶卷 (TR) |
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ADT7463
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43
Table 64. REGISTER 0X62 ENHANCED ACOUSTICS REGISTER 1 (POWERON DEFAULT = 0X00) (Note 1)
Bit
Name
R/W
Description
<2:0>
ACOU
R/W
These bits select the ramp rate applied to the PWM1 output. Instead of PWM1 jumping
instantaneously to its newly calculated speed, PWM1 ramps gracefully at the rate determined
by these bits. This feature enhances the acoustics of the fan being driven by the PWM1 output.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
11.8 sec
011 = 4
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
<3>
EN1
R/W
When this bit is 1, acoustic enhancement is enabled on PWM1 output.
<4>
SYNC
R/W
SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3.
This allows up to three fans to be driven from PWM3 output and their speeds to be measured.
SYNC = 0, only TACH3 and TACH4 are synchronized to PWM3 output.
<5>
MIN1
R/W
When the ADT7463 is in automatic fan control mode, this bit defines whether PWM1 is off
(0% duty cycle) or at PWM1 minimum duty cycle when the controlling temperature is below its
T
MIN
Hysteresis value.
0 = 0% Duty Cycle below T
MIN
Hysteresis
1 = PWM1 Minimum Duty Cycle below T
MIN
Hysteresis
<6>
MIN2
R/W
When the ADT7463 is in automatic fan speed control mode, this bit defines whether PWM2 is
off (0% duty cycle) or at PWM2 minimum duty cycle when the controlling temperature is below
its T
MIN
Hysteresis value.
0 = 0% Duty Cycle below T
MIN
Hysteresis
1 = PWM2 Minimum Duty Cycle below T
MIN
Hysteresis
<7>
MIN3
R/W
When the ADT7463 is in automatic fan speed control mode, this bit defines whether PWM3 is
off (0% duty cycle) or at PWM3 minimum duty cycle when the controlling temperature is below
its T
MIN
Hysteresis value.
0 = 0% Duty Cycle below T
MIN
Hysteresis
1 = PWM3 Minimum Duty Cycle below T
MIN
Hysteresis
1. This register becomes readonly when the Configuration Register 1 Lock bit is set to 1. Further attempts to write to this register have no effect.
Table 65. REGISTER 0X63 ENHANCED ACOUSTICS REGISTER 2 (POWERON DEFAULT = 0X00) (Note 1)
Bit
Name
R/W
Description
<2:0>
ACOU3
R/W
These bits select the ramp rate applied to the PWM3 output. Instead of PWM3 jumping
instantaneously to its newly calculated speed, PWM3 ramps gracefully at the rate determined
by these bits. This effect enhances the acoustics of the fan being driven by the PWM3 output.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
11.8 sec
011 = 4
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
<3>
EN3
R/W
When this bit is 1, acoustic enhancement is enabled on PWM3 output.
<6:4>
ACOU2
R/W
These bits select the ramp rate applied to the PWM2 output. Instead of PWM2 jumping
instantaneously to its newly calculated speed, PWM2 ramps gracefully at the rate determined
by these bits. This effect enhances the acoustics of the fans being driven by the PWM2 output.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
11.8 sec
011 = 4
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
<7>
EN2
R/W
When this bit is 1, acoustic enhancement is enabled on PWM2 output.
1. This register becomes readonly when the Configuration Register 1 Lock bit is set to 1. Further attempts to write to this register have no effect.
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