參數(shù)資料
型號(hào): ADT7463ARQZ-REEL
廠(chǎng)商: ON Semiconductor
文件頁(yè)數(shù): 40/50頁(yè)
文件大小: 726K
描述: IC REMOTE THERMAL CTRLR 24-QSOP
產(chǎn)品變化通告: MFG CHG Notification ADI to ON Semi
QSOP 24ld Pkg (MSL) Change 17/Jun/2010
標(biāo)準(zhǔn)包裝: 2,500
系列: dBCool®
功能: 風(fēng)扇控制,溫度監(jiān)控器
傳感器類(lèi)型: 內(nèi)部和外部
感應(yīng)溫度: -40°C ~ 120°C,外部傳感器
精確度: ±1.5°C(最小值)
拓?fù)洌?/td> ADC,比較器,風(fēng)扇速度計(jì)數(shù)器,多路復(fù)用器,寄存器庫(kù)
輸出類(lèi)型: SMBus?
輸出警報(bào): 無(wú)
輸出風(fēng)扇:
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 120°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-QSOP
包裝: 帶卷 (TR)
ADT7463
http://onsemi.com
40
Table 55. REGISTER 0X42  INTERRUPT STATUS REGISTER 2 (POWERON DEFAULT = 0X00)
Bit
Name
R/W
Description
<0>
12V/VC
Readonly
A one indicates the 12 V high or low limit has been exceeded. This bit gets cleared on a read of
the status register only if the error condition has subsided. If Pin 21 is configured as VID5, this
bit is the VID change bit. This bit gets set when the levels on VID0 to VID5 are different than
they were 11 ms previously. This can be used to generate an SMBALERT
 whenever the VID
code changes.
<1>
OVT
Readonly
A 1 indicates that one of the THERM
 overtemperature limits has been exceeded. This bit is
cleared on a read of the status register when the temperature drops below THERM
  T
HYST
.
<2>
FAN1
Readonly
A 1 indicates that Fan 1 has dropped below minimum speed or has stalled. This bit is NOT set
when the PWM1 output is off.
<3>
FAN2
Readonly
A 1 indicates that Fan 2 has dropped below minimum speed or has stalled. This bit is NOT set
when the PWM2 output is off.
<4>
FAN3
Readonly
A 1 indicates that Fan 3 has dropped below minimum speed or has stalled. This bit is NOT set
when the PWM3 output is off.
<5>
F4P
Readonly
A 1 indicates that Fan 4 has dropped below minimum speed or has stalled. This bit is NOT set
when the PWM3 output is off.
If Pin 14 or Pin 20 is configured as the THERM
 timer input for THERM
 monitoring, this bit is set
when the THERM
 assertion time exceeds the limit programmed in the THERM
 Limit Register
(Reg. 0x7A).
<6>
D1
Readonly
A 1 indicates either an open or short circuit on the Thermal Diode 1 inputs.
<7>
D2
Readonly
A 1 indicates either an open or short circuit on the Thermal Diode 2 inputs.
Table 56. REGISTER 0X43  VID REGISTER (POWERON DEFAULT = 0X00)
Bit
Name
R/W
Description
<4:0>
VID[4:0]
Readonly
The VID[4:0] inputs from the CPU to indicate the expected processor core voltage. On
powerup, these bits reflect the state of the VID pins even if monitoring is not enabled.
<5>
VID5
Readonly
Reads VID5 from the CPU when Bit 7 = 1. If Bit 7 = 0, then the VID5 bit always reads back 0
(poweron default).
<6>
THLD
R/W
This selects the input switching threshold for the VID inputs. THLD = 0 selects a threshold of
1 V (V
OL
< 0.8 V, V
IH
> 1.7 V). THLD = 1 lowers the switching threshold to 0.6 V (V
OL
< 0.4 V,
V
IH
> 0.8 V).
<7>
VIDSEL
R/W
VIDSEL = 0 configures Pin 21 as the 12 V measurement input (default).
VIDSEL = 1 configures Pin 21 as the VID5 input. This also allows VID code changes to be
detected.
Table 57. VOLTAGE LIMIT REGISTERS (Note 1)
Register Address
R/W
Description (Note 2)
PowerOn Default
0x44
R/W
2.5 V Low Limit
0x00
0x45
R/W
2.5 V High Limit
0xFF
0x46
R/W
V
CCP
 Low Limit
0x00
0x47
R/W
V
CCP
 High Limit
0xFF
0x48
R/W
V
CC
 Low Limit
0x00
0x49
R/W
V
CC
 High Limit
0xFF
0x4A
R/W
5 V Low Limit
0x00
0x4B
R/W
5 V High Limit
0xFF
0x4C
R/W
12 V Low Limit
0x00
0x4D
R/W
12 V High Limit
0xFF
1.  Setting the Configuration Register 1 Lock bit has no effect on these registers.
2.  High limits: an interrupt is generated when a value exceeds its high limit (> comparison); Low limits: an interrupt is generated when a value
is equal to or below its low limit (d comparison).
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