參數(shù)資料
型號: ADT7463ARQZ-REEL
廠商: ON Semiconductor
文件頁數(shù): 12/50頁
文件大?。?/td> 726K
描述: IC REMOTE THERMAL CTRLR 24-QSOP
產(chǎn)品變化通告: MFG CHG Notification ADI to ON Semi
QSOP 24ld Pkg (MSL) Change 17/Jun/2010
標準包裝: 2,500
系列: dBCool®
功能: 風扇控制,溫度監(jiān)控器
傳感器類型: 內(nèi)部和外部
感應溫度: -40°C ~ 120°C,外部傳感器
精確度: ±1.5°C(最小值)
拓撲: ADC,比較器,風扇速度計數(shù)器,多路復用器,寄存器庫
輸出類型: SMBus?
輸出警報:
輸出風扇:
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 120°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 24-QSOP
包裝: 帶卷 (TR)
ADT7463
http://onsemi.com
12
clock pulse, known as the Acknowledge Bit. All
other devices on the bus now remain idle while the
selected device waits for data to be read from or
written to it. If the R/W
 bit is a 0, then the master
writes to the slave device. If the R/W
 bit is a 1, the
master reads from the slave device.
2. Data is sent over the serial bus in sequences of
nine clock pulses, eight bits of data followed by an
Acknowledge Bit from the slave device.
Transitions on the data line must occur during the
low period of the clock signal and remain stable
during the high period, as a lowtohigh transition
when the clock is high may be interpreted as a
STOP signal. The number of data bytes that can be
transmitted over the serial bus in a single READ or
WRITE operation is limited only by what the
master and slave devices can handle.
3. When all data bytes have been read or written,
stop conditions are established. In WRITE mode,
the master pulls the data line high during the tenth
clock pulse to assert a STOP condition. In READ
mode, the master device overrides the
acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse.
This is known as No Acknowledge. The master
then takes the data line low during the low period
before the 10th clock pulse, and then high during
the 10th clock pulse to assert a STOP condition.
Any number of bytes of data can be transferred over the
serial bus in one operation, but it is not possible to mix read
and write in one operation because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation.
In the case of the ADT7463, write operations contain
either one or two bytes, and read operations contain one byte
and perform the following functions.
To write data to one of the device data registers or read
data from it, the address pointer register must be set so that
the correct data register is addressed, then data can be written
into that register or read from it. The first byte of a write
operation always contains an address that is stored in the
address pointer register. If data is to be written to the device,
then the write operation contains a second data byte that is
written to the register selected by the address pointer
register.
This is illustrated in Figure 17. The device address is sent
over the bus followed by R/W
 being set to 0. This is followed
by two data bytes. The first data byte is the address of the
internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to
be written to the internal data register.
Figure 17. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
R/W
SCL
SDA
1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7463
START BY
MASTER
1
9
1
ACK. BY
ADT7463
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7463
STOP BY
MASTER
1
9
SCL (CONTINUED)
SDA (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
1
0
1
0
Figure 18. Writing to the Address Pointer Register Only
SCL
SDA
1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7463
START BY
MASTER
1
9
1
ACK. BY
ADT7463
9
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
R/W
1
0
1
0
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