參數(shù)資料
型號(hào): ADT7463ARQZ-REEL
廠商: ON Semiconductor
文件頁(yè)數(shù): 15/50頁(yè)
文件大?。?/td> 726K
描述: IC REMOTE THERMAL CTRLR 24-QSOP
產(chǎn)品變化通告: MFG CHG Notification ADI to ON Semi
QSOP 24ld Pkg (MSL) Change 17/Jun/2010
標(biāo)準(zhǔn)包裝: 2,500
系列: dBCool®
功能: 風(fēng)扇控制,溫度監(jiān)控器
傳感器類型: 內(nèi)部和外部
感應(yīng)溫度: -40°C ~ 120°C,外部傳感器
精確度: ±1.5°C(最小值)
拓?fù)洌?/td> ADC,比較器,風(fēng)扇速度計(jì)數(shù)器,多路復(fù)用器,寄存器庫(kù)
輸出類型: SMBus?
輸出警報(bào): 無(wú)
輸出風(fēng)扇:
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 120°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-QSOP
包裝: 帶卷 (TR)
ADT7463
http://onsemi.com
15
Associated with each voltage measurement channel are
high and low limit registers. Exceeding the programmed
high or low limit causes the appropriate status bit to be set.
Exceeding either limit can also generate SMBALERT
interrupts.
Table 8. VOLTAGE MEASUREMENT LIMITS
REGISTERS
Register
Description
Default
0x44
2.5 V Low Limit
0x00
0x45
2.5 V High Limit
0xFF
0x46
V
CCP
 Low Limit
0x00
0x47
V
CCP
 High Limit
0xFF
0x48
V
CC
 Low Limit
0x00
0x49
V
CC
 High Limit
0xFF
0x4A
5 V Low Limit
0x00
0x4B
5 V High Limit
0xFF
0x4C
12 V Low Limit
0x00
0x4D
12 V High Limit
0xFF
Figure 23. Structure of Analog Inputs
120 kW
20 kW
12 V
IN
30 pF
93 kW
47 kW
5 V
IN
30 pF
68 kW
71 kW
3.3 V
IN
30 pF
45 kW
94 kW
2.5 V
IN
30 pF
17.5 kW
52.5 kW
V
CCP
35 pF
MUX
Table 12 shows the input ranges of the analog inputs and
output codes of the 10bit ADC.
When the ADC is running, it samples and converts a
voltage input in 711 ms and averages 16 conversions to
reduce noise; a measurement on each input takes nominally
11.38 ms.
VID Code Monitoring
The ADT7463 has five dedicated voltage ID (VID code)
inputs. These are digital inputs that can be read back through
the VID register (Reg. 0x43) to determine the processor
voltage required/being used in the system. Five VID code
inputs support VRM9.x solutions. In addition, Pin 21 (12 V
input) can be reconfigured as a sixth VID input to satisfy
future VRM requirements.
Table 9. VID CODE REGISTER (REG. 0X43)
Bit
Description
<0> VID0
Reflects Logic State of Pin 5
<1> VID1
Reflects Logic State of Pin 6
<2> VID2
Reflects Logic State of Pin 7
<3> VID3
Reflects Logic State of Pin 8
<4> VID4
Reflects Logic State of Pin 19
<5> VID5
Reconfigurable 12 V Input. This bit reads 0
when Pin 21 is configured as the 12 V input.
This bit reflects the logic state of Pin 21 when
the pin is configured as VID5.
VID Code Input Threshold Voltage
The switching threshold for the VID code inputs is
approximately 1 V. To enable future compatibility, it is
possible to reduce the VID code input threshold to 0.6 V.
Bit 6 (THLD) of VID register (Reg. 0x43) controls the VID
input threshold voltage.
Table 10. VID CODE REGISTER (REG. 0X43)
Bit
Description
<6>
THLD
0: VID Switching Threshold = 1 V,
V
OL
< 0.8 V, V
IH
> 1.7 V, V
MAX
= 3.3 V
1: VID Switching Threshold = 0.6 V,
V
OL
< 0.4 V, V
IH
> 0.8 V, V
MAX
= 3.3 V
Reconfiguring Pin 21 (+12V/VID5) as VID5 Input
Pin 21 can be reconfigured as a sixth VID code input
(VID5) for VRM10compatible systems. Since the pin is
configured as VID5, it is no longer possible to monitor a
12 V supply.
Bit 7 of the VID register (Reg. 0x43) determines the
function of Pin 21. System or BIOS software can read the
state of Bit 7 to determine whether the system is designed to
monitor 12 V or is monitoring a sixth VID input.
Table 11. VID CODE REGISTER (REG. 0X43)
Bit
Description
<7>
VIDSEL
0: Pin 21 functions as a 12 V measurement
input. Software can read this bit to determine
that there are five VID inputs being monitored.
Bit 5 of Register 0x43 (VID5) always reads
back 0. Bit 0 of Status Register 2 (Reg. 0x42)
reflects 12 V outoflimit measurements.
1: Pin 21 functions as the sixth VID code input
(VID5). Software can read this bit to determine
that there are six VID inputs being monitored.
Bit 5 of Register 0x43 reflects the logic state of
Pin 21. Bit 0 of Status Register 2 (Reg. 0x42)
reflects VID code changes.
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