參數(shù)資料
型號： ADT7463ARQZ-REEL
廠商： ON Semiconductor
文件頁數(shù)： 26/50頁
文件大?。?/td> 726K
描述： IC REMOTE THERMAL CTRLR 24-QSOP
產(chǎn)品變化通告： MFG CHG Notification ADI to ON Semi
QSOP 24ld Pkg (MSL) Change 17/Jun/2010
標準包裝： 2,500
系列： dBCool®
功能： 風扇控制，溫度監(jiān)控器
傳感器類型： 內(nèi)部和外部
感應(yīng)溫度： -40°C ~ 120°C，外部傳感器
精確度： ±1.5°C（最小值）
拓撲： ADC，比較器，風扇速度計數(shù)器，多路復(fù)用器，寄存器庫
輸出類型： SMBus?
輸出警報： 無
輸出風扇： 是
電源電壓： 3 V ~ 5.5 V
工作溫度： -40°C ~ 120°C
安裝類型： 表面貼裝
封裝/外殼： 24-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 24-QSOP
包裝： 帶卷 (TR)
ADT7463
http://onsemi.com
26
Figure 38 is a Functional Block Diagram of the THERM
timer, limit, and associated circuitry. Writing a value of 0x00
to   the   THERM
   limit   register   (Reg. 0x7A)   causes
SMBALERT
 to be generated on the first THERM
 assertion.
A THERM
 limit value of 0x01 generates an SMBALERT
once cumulative THERM
 assertions exceed 45.52 ms.
Configuring the Desired THERM
 Behavior
1. Configure the desired pin as the THERM
 input:
Setting Bit 1 (THERM
 Enable) of Configuration
Register 3 (Reg. 0x78) enables the THERM
monitoring functionality. This is enabled on Pin 14
by default.
Setting Bit 1 (TH5V) of Configuration Register 4
(Reg. 0x7D) enables THERM
 monitoring on
Pin 20 (Bit 1 of Configuration Register 3 must also
be set). Pin 14 can be used as TACH4.
2. Select the desired fan behavior for THERM
events:
Setting Bit 2 (BOOST bit) of Configuration
Register 3 (Reg. 0x78) causes all fans to run at
100% duty cycle whenever THERM
 gets asserted.
This allows failsafe system cooling. If this
bit = 0, the fans run at their current settings and are
not affected by THERM
 events.
3. Select whether THERM
 events should generate
SMBALERT
 interrupts:
Bit 5 (F4P) of Mask Register 2 (Reg. 0x75), when
set, masks out SMBALERT
s when the THERM
limit value gets exceeded. This bit should be
cleared if SMBALERT
s based on THERM
 events
are required.
4. Select a suitable THERM
 limit value:
This value determines whether an SMBALERT
 is
generated on the first THERM
 assertion, or only if
a cumulative THERM
 assertion time limit is
exceeded. A value of 0x00 causes an SMBALERT
to be generated on the first THERM
 assertion.
5. Select a THERM
 monitoring time:
This is how often OS or BIOS level software
checks the THERM
 timer. For example, BIOS
could read the THERM
 timer once an hour to
determine the cumulative THERM
 assertion time.
If, for example, the total THERM
 assertion time is
<22.76 ms in Hour 1, >182.08 ms in Hour 2, and
>5.825 s in Hour 3, this can indicate that system
performance is degrading significantly since
THERM
 is asserting more frequently on an hourly
basis.
Alternatively, OS or BIOS level software can
timestamp when the system is powered on. If an
SMBALERT
 is generated due to the THERM
 limit
being exceeded, another timestamp can be taken.
The difference in time can be calculated for a fixed
THERM
 limit time. For example, if it takes one
week for a THERM
 limit of 2.914 s to be
exceeded and the next time it takes only 1 hour,
then this is an indication of a serious degradation
in system performance.
Configuring the ADT7463 THERM
 Pin as an Output
In addition to the ADT7463 being able to monitor
THERM
 as an input, the ADT7463 can optionally drive
THERM
 low as an output. The user can preprogram system
critical thermal limits. If the temperature exceeds a thermal
limit by 0.25癈, THERM
 asserts low. If the temperature is
still above the thermal limit on the next monitoring cycle,
THERM
 stays low. THERM
 remains asserted low until the
temperature is equal to or below the thermal limit. Since the
temperature for that channel is measured only every
monitoring cycle, once THERM
 asserts it is guaranteed to
remain low for at least one monitoring cycle.
The THERM
 pin can be configured to assert low if the
Remote 1, Local, or Remote 2 Temperature THERM
 limits
get exceeded by 0.25癈. The THERM
 limit registers are at
locations 0x6A, 0x6B, and 0x6C, respectively. Setting Bit 3
of Registers 0x5F, 0x60, and 0x61 enables the THERM
output feature for the Remote 1, Local, and Remote 2
Temperature channels, respectively. Figure 39 shows how
the THERM
 pin asserts low as an output in the event of a
critical overtemperature.
Figure 39. Asserting THERM
 as an Output, Based on
Tripping THERM
 Limits
THERM
 LIMIT
ADT7463
MONITORING
CYCLE
TEMP
THERM
+0.255C
THERM
 LIMIT
Fan Drive Using PWM Control
The ADT7463 uses pulsewidth modulation (PWM) to
control fan speed. This relies on varying the duty cycle (or
on/off ratio) of a square wave applied to the fan to vary the
fan speed. The external circuitry required to drive a fan using
PWM control is extremely simple. A single NMOSFET is
the only drive device required. The specifications of the
MOSFET depend on the maximum current required by the
fan being driven. Typical notebook fans draw a nominal
170 mA, and so SOT devices can be used where board space
is a concern. In desktops, fans can typically draw 250 mA to
300 mA each. If you drive several fans in parallel from a
single PWM output or drive larger server fans, the MOSFET
needs to handle the higher current requirements. The only
other stipulation is that the MOSFET should have a gate
voltage drive, V
GS
< 3.3 V for direct interfacing to the
PWM_OUT pin. V
GS
 can be greater than 3.3 V as long as the
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