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參數(shù)資料
| 型號： | ADSP-BF547YBCZ-4A |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 90/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP BLACKFIN 400MHZ 400CSPBGA |
| 標準包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點 |
| 接口： | SPI，SSP，TWI，UART，USB |
| 時鐘速率： | 400MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 260kB |
| 電壓 - 輸入/輸出： | 2.50V，3.30V |
| 電壓 - 核心： | 1.25V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-LFBGA，CSPBGA |
| 供應商設備封裝： | 400-CSPBGA（17x17） |
| 包裝： | 托盤 |
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ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. D
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Page 9 of 100
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May 2011
SIC interrupt mask registers (SIC_IMASKx). These regis-
ters control the masking and unmasking of each peripheral
interrupt event. When a bit is set in a register, that periph-
eral event is unmasked and is processed by the system
when asserted. A cleared bit in the register masks the
peripheral event, preventing the processor from servicing
the event.
SIC interrupt status registers (SIC_ISRx). As multiple
peripherals can be mapped to a single event, these registers
allow the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.
SIC interrupt wakeup enable registers (SIC_IWRx). By
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled or in Sleep mode when the event is generated.
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected. (Detection requires two core clock cycles.) The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC recognizes and queues the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
DMA CONTROLLERS
ADSP-BF54x Blackfin processors have multiple, independent
DMA channels that support automated data transfers with min-
imal overhead for the processor core. DMA transfers can occur
between the ADSP-BF54x processors’ internal memories and
any of the DMA-capable peripherals. Additionally, DMA trans-
fers can be accomplished between any of the DMA-capable
peripherals and external devices connected to the external
memory interfaces, including DDR and asynchronous memory
controllers.
While the USB controller and MXVR have their own dedicated
DMA controllers, the other on-chip peripherals are managed by
two centralized DMA controllers, called DMAC1 (32-bit) and
DMAC0 (16-bit). Both operate in the SCLK domain. Each DMA
controller manages 12 independent peripheral DMA channels,
as well as two independent memory DMA streams. The
DMAC1 controller masters high-bandwidth peripherals over a
dedicated 32-bit DMA access bus (DAB32). Similarly, the
DMAC0 controller masters most serial interfaces over the 16-bit
DAB16 bus. Individual DMA channels have fixed access prior-
ity on the DAB buses. DMA priority of peripherals is managed
by a flexible peripheral-to-DMA channel assignment scheme.
All four DMA controllers use the same 32-bit DCB bus to
exchange data with L1 memory. This includes L1 ROM, but
excludes scratchpad memory. Fine granulation of L1 memory
and special DMA buffers minimize potential memory conflicts
when the L1 memory is accessed simultaneously by the core.
Similarly, there are dedicated DMA buses between the external
bus interface unit (EBIU) and the three DMA controllers
(DMAC1, DMAC0, and USB) that arbitrate DMA accesses to
external memories and the boot ROM.
The ADSP-BF54x Blackfin processors’ DMA controllers sup-
port both 1-dimensional (1D) and 2-dimensional (2D) DMA
transfers. DMA transfer initialization can be implemented from
registers or from sets of parameters called descriptor blocks.
The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.
Examples of DMA types supported by the ADSP-BF54x Black-
fin processors’ DMA controllers include:
A single, linear buffer that stops upon completion
A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
1D or 2D DMA using a linked list of descriptors
2D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, the
DMAC1 and DMAC0 controllers each feature two memory
DMA channel pairs for transfers between the various memories
of the ADSP-BF54x Blackfin processors. This enables transfers
of blocks of data between any of the memories—including
external DDR, ROM, SRAM, and flash memory—with minimal
processor intervention. Like peripheral DMAs, memory DMA
transfers can be controlled by a very flexible descriptor-based
methodology or by a standard register-based autobuffer
mechanism.
The memory DMA channels of the DMAC1 controller
(MDMA2 and MDMA3) can be controlled optionally by the
external DMA request input pins. When used in conjunction
with the External Bus Interface Unit (EBIU), this handshaked
memory DMA (HMDMA) scheme can be used to efficiently
exchange data with block-buffered or FIFO-style devices con-
nected externally. Users can select whether the DMA request
pins control the source or the destination side of the memory
DMA. It allows control of the number of data transfers for
memory DMA. The number of transfers per edge is program-
mable. This feature can be programmed to allow memory DMA
to have an increased priority on the external bus relative to the
core.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ADSP-BF548BBCZ | 制造商:Analog Devices 功能描述: |
| ADSP-BF548BBCZ-5A | 功能描述:IC DSP 16BIT 533MHZ 400CSBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF548BBCZ-5AA | 功能描述:IC DSP 16BIT 533MHZ 400CSBGA 制造商:analog devices inc. 系列:Blackfin? 包裝:托盤 零件狀態(tài):有效 類型:定點 接口:CAN，SPI，SSP，TWI，UART，USB 時鐘速率:533MHz 非易失性存儲器:外部 片載 RAM:260kB 電壓 - I/O:2.50V，3.30V 電壓 - 內(nèi)核:1.25V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:表面貼裝 封裝/外殼:400-LFBGA，CSPBGA 供應商器件封裝:400-CSPBGA（17x17） 標準包裝:1 |
| ADSP-BF548BBCZ-5X | 制造商:Analog Devices 功能描述:- Trays |
| ADSP-BF548MBBCZ-5M | 功能描述:IC DSP 533MHZ W/DDR 400CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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