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Rev. D
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Page 22 of 100
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May 2011
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
MXI driven with external clock oscillator IC:
MXI should be driven with the clock output of a clock
oscillator IC running at a frequency of 49.152 MHz or
45.1584 MHz.
MXO should be left unconnected.
Avoid routing other switching signals near the oscillator
and clock output trace to avoid crosstalk. When not possi-
ble, shield traces with ground.
MXI/MXO with external crystal:
The crystal must be a fundamental mode crystal running at
a frequency of 49.152 MHz or 45.1584 MHz.
The crystal and load capacitors should be placed physically
close to the MXI and MXO pins on the board.
Board trace capacitance on each lead should not be more
than 3 pF.
Trace capacitance plus load capacitance should equal the
load capacitance specification for the crystal.
Avoid routing other switching signals near the crystal and
components to avoid crosstalk. When not possible, shield
traces and components with ground.
VDDMP/GNDMP—MXVR PLL power domain:
Route VDDMP and GNDMP with wide traces or as isolated
power planes.
Drive VDDMP to same level as VDDINT.
Place a ferrite bead between the VDDINT power plane and the
VDDMP pin for noise isolation.
Locally bypass VDDMP with 0.1 μF and 0.01 μF decoupling
capacitors to GNDMP.
Avoid routing switching signals near to VDDMP and GNDMP
traces to avoid crosstalk.
Fiber optic transceiver (FOT) connections:
Keep the traces between the ADSP-BF549 processor and
the FOT as short as possible.
The receive data trace connecting the FOT receive data
output pin to the ADSP-BF549 PH6/MRX input pin should
have a 0 Ω series termination resistor placed close to the
FOT receive data output pin. Typically, the edge rate of the
FOT receive data signal driven by the FOT is very slow, and
further degradation of the edge rate is not desirable.
The transmit data trace connecting the ADSP-BF549
PH5/MTX output pin to the FOT transmit data input pin
should have a 27 Ω series termination resistor placed close
to the ADSP-BF549 PH5/MTX pin.
The receive data trace and the transmit data trace between
the ADSP-BF549 processor and the FOT should not be
routed close to each other in parallel over long distances to
avoid crosstalk.
RELATED DOCUMENTS
ADSP-BF54x Blackfin Processor Hardware Reference, Vol-
ume 1 and Volume 2
Blackfin Processor Programming Reference
ADSP-BF542/BF544/BF547/BF548/BF549
Blackfin Anomaly List
RELATED SIGNAL CHAINS
A signal chain is a series of signal-conditioning electronic com-
ponents that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the "signal chain" entry in
website.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
The Application Signal Chains page in the Circuits from the
Lab
Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
Drill down links for components in each chain to selection
guides and application information
Reference designs applying best practice design techniques
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