參數(shù)資料
型號: ADSP-BF535PKBZ-350
廠商: Analog Devices Inc
文件頁數(shù): 8/44頁
文件大小: 0K
描述: IC DSP CONTROLLER 16BIT 260-BGA
產(chǎn)品培訓模塊: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標準包裝: 1
系列: Blackfin®
類型: 定點
接口: PCI,SPI,SSP,UART,USB
時鐘速率: 350MHz
非易失內(nèi)存: 外部
芯片上RAM: 308kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.60V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 260-BBGA
供應商設備封裝: 260-PBGA(19x19)
包裝: 托盤
ADSP-BF535
–16–
REV. A
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide range
of tools supporting the Blackfin processor family. Third Party
software tools include DSP libraries, real-time operating systems,
and block diagram design tools.
EZ-KIT Lite
for ADSP-BF535 Blackfin Processor
The EZ-KIT Lite provides developers with a cost-effective
method for initial evaluation of the ADSP-BF535 Blackfin pro-
cessor. The EZ-KIT Lite includes a desktop evaluation board
and fundamental debugging software to facilitate architecture
evaluations via a PC hosted toolset. With the EZ-KIT Lite, users
can learn more about Analog Devices hardware and software
development tools and prototype applications. The EZ-KIT Lite
includes an evaluation suite of the VisualDSP++ development
environment with C/C++ compiler, assembler, and linker. The
VisualDSP++ software included with the kit is limited in program
memory size and limited to use with the EZ-KIT Lite product.
Designing an Emulator Compatible
Processor Board (Target)
The Analog Devices family of emulators are tools that every
system developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test
Access Port (TAP) on the ADSP-BF535 Blackfin processor. The
emulator uses the TAP to access the internal features of the pro-
cessor, allowing the developer to load code, set breakpoints,
observe variables, observe memory, and examine registers. The
processor must be halted to send data and commands, but once
an operation has been completed by the emulator, the processor
system is set running at full speed with no impact on system
timing.
To use these emulators, the target’s design must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including single
processor connections, multiprocessor scan chains, signal buff-
ering, signal termination, and emulator pod logic, see the EE-68:
Analog Devices
JTAG Emulation Technical Reference on the Analog
Devices website (www.analog.com)—use site search on
“EE-68”. This document is updated regularly to keep pace with
improvements to emulator support.
Additional Information
This data sheet provides a general overview of the ADSP-BF535
Blackfin processor architecture and functionality. For detailed
information on the Blackfin processor family core architecture
and instruction set, refer to the ADSP-BF535 Blackfin Processor
Hardware Reference and the Blackfin Processor Instruction Set
Reference.
EZ-KIT Lite is a trademark of Analog Devices, Inc.
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