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參數資料
| 型號： | ADSP-BF535PKBZ-350 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 31/44頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 260-BGA |
| 產品培訓模塊： | Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 標準包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點 |
| 接口： | PCI，SPI，SSP，UART，USB |
| 時鐘速率： | 350MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 308kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.60V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 260-BBGA |
| 供應商設備封裝： | 260-PBGA（19x19） |
| 包裝： | 托盤 |
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–37–
REV. A
ADSP-BF535
The frequency f includes driving the load high and then back low.
For example: DATA31–0 pins can drive high and low at a
maximum rate of 1/(2
tSCLK) while in SDRAM burst mode.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
Note that the conditions causing a worst-case PEXT differ from
those causing a worst-case P
INT . Maximum PINT cannot occur
while 100% of the output pins are switching from all ones (1s) to
all zeros (0s). Note, as well, that it is not common for an appli-
cation to have 100% or even 50% of the outputs switching
simultaneously.
Test Conditions
All timing parameters appearing in this data sheet were measured
under the conditions described in this section.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time tENA is the interval from the
point when a reference signal reaches a high or low voltage level
to the point when the output starts driving as shown in the Output
the interval from when the reference signal switches to when the
output voltage reaches 2.0 V (output high) or 1.0 V (output low).
Time tTRIP is the interval from when the output starts driving to
when the output reaches the 1.0 V or 2.0 V trip voltage. Time
tENA is calculated as shown in the equation:
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
Output Disable Time
Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by
V is dependent on the capacitive load, C
L and the
load current, IL. This decay time can be approximated by the
equation:
The output disable time tDIS is the difference between
tDIS_MEASURED is the interval from when the reference signal
switches to when the output voltage decays
V from the measured
output high or output low voltage. The time tDECAY is calculated
with test loads CL and IL, and with
V equal to 0.5 V.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose
V
to be the difference between the ADSP-BF535 Blackfin proces-
sor’s output voltage and the input threshold for the device
requiring the hold time. A typical
V will be 0.4 V. C
L is the total
bus capacitance (per data line), and IL is the total leakage or three-
state current (per data line). The hold time will be tDECAY plus the
minimum disable time (for example, tDSDAT for an SDRAM write
cycle).
Table 27. PLL Power Dissipation
Parameter
Test Conditions
Typical
Unit
IDDPLL
VDDPLL=1.5 V, 25C
4.0
mA
PTOTAL
PEXT
I
( DD VDDINT
×)
+
=
tENA tENA_MEASURED
=
tTRIP
–
tDECAY
CLV
() IL
=
Figure 22. Output Enable/Disable
Figure 23. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
Figure 24. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS DRIVING
VOH (MEASURED)
V
VOL (MEASURED) + V
tDIS_MEASURED
VOH
(MEASURED)
VOL
(MEASURED)
2.0V
1.0V
VOH
(MEASURED)
VOL
(MEASURED)
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
OUTPUT STOPS DRIVING
tENA
tDECAY
tENA-MEASURED
tTRIP
1.5V
30pF
TO
OUTPUT
PIN
50
INPUT
OR
OUTPUT
1.5V
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