- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗19481 > ADSP-BF506BSWZ-4F (Analog Devices Inc)IC DSP 400MHZ 1.4V 120LQFP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | ADSP-BF506BSWZ-4F |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 61/80闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DSP 400MHZ 1.4V 120LQFP |
| 瑕栭牷鏂囦欢锛� | Blackfin? BF50x Processor Family |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | Blackfin® |
| 椤炲瀷锛� | 瀹氶粸(di菐n) |
| 鎺ュ彛锛� | CAN锛孍BI/EMI锛孖²C锛孖rDA锛孭PI锛孲PI锛孲PORT锛孶ART/USART |
| 鏅�(sh铆)閻橀€熺巼锛� | 400MHz |
| 闈炴槗澶卞収(n猫i)瀛橈細 | 闁冨瓨锛�16MB锛� |
| 鑺墖涓奟AM锛� | 68kB |
| 闆诲 - 杓稿叆/杓稿嚭锛� | 3.30V |
| 闆诲 - 鏍稿績锛� | 1.29V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 120-LQFP 瑁搁湶鐒婄洡 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 120-LQFP-EP锛�14x14锛� |
| 鍖呰锛� | 鎵樼洡 |
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Rev. A
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Page 64 of 80
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July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
supply using the 0 to VREF range or 2 脳 VREF range, respectively.
The common mode must be in this range to guarantee the func-
tionality of the ADC.
When a conversion takes place, the common mode is rejected,
resulting in a virtually noise free signal of amplitude 鈥揤REF to
+VREF corresponding to the digital codes of 0 to 4096. If the 2 脳
VREF range is used, then the input signal amplitude extends from
鈥� 2 VREF to +2 VREF after conversion.
Driving Differential Inputs
Differential operation requires that VIN+ and VIN鈥� be simultane-
ously driven with two equal signals that are 180掳 out of phase.
The common mode must be set up externally. The common-
mode range is determined by VREF, the power supply, and the
particular amplifier used to drive the analog inputs. Differential
modes of operation with either an ac or dc input provide the
best THD performance over a wide frequency range. Because
not all applications have a signal preconditioned for differential
operation, there is often a need to perform single-ended-to-dif-
ferential conversion.
Using an Op Amp Pair
An op amp pair can be used to directly couple a differential sig-
nal to one of the analog input pairs of the ADC. The circuit
configurations illustrated in Figure 72 (Dual Op Amp Circuit to
how a dual op amp can be used to convert a single-ended signal
into a differential signal for both a bipolar and unipolar input
signal, respectively.
The voltage applied to Point A sets up the common-mode volt-
age. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. The AD8022 is a suit-
able dual op amp that can be used in this configuration to
provide differential drive to the ADC.
Take care when choosing the op amp; the selection depends on
the required power supply and system performance objectives.
The driver circuits in Figure 72 (Dual Op Amp Circuit to Con-
Bipolar Signal into a Differential Unipolar Signal) are optimized
for dc coupling applications requiring best distortion
performance.
The circuit configuration shown in Figure 72 (Dual Op Amp
ential Signal) converts a unipolar, single-ended signal into a
differential signal.
Differential Unipolar Signal) is configured to convert and level
shift a single-ended, ground-referenced (bipolar) signal to a dif-
ferential signal centered at the VREF level of the ADC.
Pseudo Differential Mode
The ADC can have a total of six pseudo differential pairs. In this
mode, VIN+ is connected to the signal source that must have an
amplitude of VREF (or 2 脳 VREF, depending on the range chosen)
Figure 70. Input Common-Mode Range vs. VREF (0 to VREF Range, VDD = 5 V)
Figure 71. Input Common-Mode Range vs. VREF (2 脳 VREF Range, VDD = 5 V)
VREF (V)
5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
COMMON-MODE
RANGE
(V)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
TA = 25掳C
VREF (V)
2.5
0
0.5
1.0
1.5
2.0
COMMON-MODE
RANGE
(V)
5.0
4.0
4.5
3.0
3.5
2.0
2.5
0.5
1.0
1.5
0
TA = 25掳C
Figure 72. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal
Into a Differential Signal
GND
2 脳 VREF p鈥損
27
V+
V鈥�
V+
V鈥�
VREF
2.5V
3.75V
1.25V
2.5V
3.75V
1.25V
VREF
(DCAPA/DCAPB)
VIN+
ADC
1
VIN鈥�
440
220
0.47渭F
1ADDITIONAL PINS OMITTED FOR CLARITY.
220
10k
A
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