參數(shù)資料
型號: ADSP-BF506BSWZ-4F
廠商: Analog Devices Inc
文件頁數(shù): 26/80頁
文件大小: 0K
描述: IC DSP 400MHZ 1.4V 120LQFP
視頻文件: Blackfin? BF50x Processor Family
標準包裝: 1
系列: Blackfin®
類型: 定點
接口: CAN,EBI/EMI,I²C,IrDA,PPI,SPI,SPORT,UART/USART
時鐘速率: 400MHz
非易失內(nèi)存: 閃存(16MB)
芯片上RAM: 68kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.29V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 120-LQFP 裸露焊盤
供應商設備封裝: 120-LQFP-EP(14x14)
包裝: 托盤
Rev. A
|
Page 32 of 80
|
July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
PROCESSOR—TIMING SPECIFICATIONS
Specifications subject to change without notice.
Clock and Reset Timing
Table 24 and Figure 10 describe clock and reset operations. Per
the CCLK and SCLK timing specifications in Table 14 to
Table 16, combinations of CLKIN and clock multipliers must
not select core/peripheral clocks in excess of the processor’s
speed grade. Table 25 and Figure 11 describe clock out timing.
Table 24. Clock and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
fCKIN
CLKIN Frequency1, 2, 3, 4 (Commercial/Industrial Models) 12
50
MHz
CLKIN Frequency1, 2, 3, 4 (Automotive Models)
14
50
MHz
tCKINL
CLKIN Low Pulse1
10
ns
tCKINH
CLKIN High Pulse
10
ns
tWRST
RESET Asserted Pulse Width Low
5
11 × tCKIN
ns
Switching Characteristic
tBUFDLAY
CLKIN to CLKBUF6 Delay
11
ns
1 Applies to PLL bypass mode and PLL non bypass mode.
2 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 14 on Page 26 through
3 The tCKIN period (see Figure 10) equals 1/fCKIN.
4 If the DF bit in the PLL_CTL register is set, the minimum f
CKIN specification is 24 MHz for commercial/industrial models and 28 MHz for automotive models.
5 Applies after power-up sequence is complete. See Table 26 and Figure 12 for power-up reset timing.
6 The ADSP-BF504/ADSP-BF504F/ADSP-BF506F processor does not have a dedicated CLKBUF pin. Rather, the EXTCLK pin may be programmed to serve as CLKBUF or
CLKOUT. This parameter applies when EXTCLK is programmed to output CLKBUF.
Figure 10. Clock and Reset Timing
CLKIN
tWRST
tCKIN
tCKINL
tCKINH
tBUFDLAY
RESET
CLKBUF
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