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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ADSP-BF506BSWZ-4F |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 27/80闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC DSP 400MHZ 1.4V 120LQFP |
| 瑕栭牷鏂囦欢锛� | Blackfin? BF50x Processor Family |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | Blackfin® |
| 椤炲瀷锛� | 瀹氶粸 |
| 鎺ュ彛锛� | CAN锛孍BI/EMI锛孖²C锛孖rDA锛孭PI锛孲PI锛孲PORT锛孶ART/USART |
| 鏅傞悩閫熺巼锛� | 400MHz |
| 闈炴槗澶卞収(n猫i)瀛橈細 | 闁冨瓨锛�16MB锛� |
| 鑺墖涓奟AM锛� | 68kB |
| 闆诲 - 杓稿叆/杓稿嚭锛� | 3.30V |
| 闆诲 - 鏍稿績锛� | 1.29V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 120-LQFP 瑁搁湶鐒婄洡 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 120-LQFP-EP锛�14x14锛� |
| 鍖呰锛� | 鎵樼洡 |
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Rev. A
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Page 33 of 80
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July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Table 25. Clock Out Timing
Parameter
V
DDEXT = 1.8 V
V
DDEXT = 2.5 V/3.3 V
Min
Max
Min
Max
Unit
Switching Characteristics
tSCLK
CLKOUT1 Period2,3
10
ns
tSCLKH
CLKOUT1 Width High
44ns
tSCLKL
CLKOUT1 Width Low
4
ns
1 The ADSP-BF504/ADSP-BF504F/ADSP-BF506F processor does not have a dedicated CLKOUT pin. Rather, the EXTCLK pin may be programmed to serve as CLKBUF or
CLKOUT. This parameter applies when EXTCLK is programmed to output CLKOUT.
2 The tSCLK value is the inverse of the fSCLK specification. Reduced supply voltages affect the best-case value of 10 ns listed here.
3 The tSCLK value does not account for the effects of jitter.
Figure 11. Clock Out Timing
t
SCLKL
t
SCLKH
t
SCLK
CLKOUT
Table 26. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
t
RST
_IN_PWR
RESET Deasserted after the V
DDINT, VDDEXT, VDDFLASH, and CLKIN Pins are Stable and
Within Specification
3500 脳 t
CKIN
ns
Figure 12. Power-Up Reset Timing
RESET
tRST_IN_PWR
CLKIN
V
DD_SUPPLIES
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