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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ADSP-BF506BSWZ-4F |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 17/80闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DSP 400MHZ 1.4V 120LQFP |
| 瑕栭牷鏂囦欢锛� | Blackfin? BF50x Processor Family |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | Blackfin® |
| 椤炲瀷锛� | 瀹氶粸 |
| 鎺ュ彛锛� | CAN锛孍BI/EMI锛孖²C锛孖rDA锛孭PI锛孲PI锛孲PORT锛孶ART/USART |
| 鏅傞悩閫熺巼锛� | 400MHz |
| 闈炴槗澶卞収(n猫i)瀛橈細 | 闁冨瓨锛�16MB锛� |
| 鑺墖涓奟AM锛� | 68kB |
| 闆诲 - 杓稿叆/杓稿嚭锛� | 3.30V |
| 闆诲 - 鏍稿績锛� | 1.29V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 120-LQFP 瑁搁湶鐒婄洡 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 120-LQFP-EP锛�14x14锛� |
| 鍖呰锛� | 鎵樼洡 |
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Rev. A
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Page 24 of 80
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July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
DOUTA, DOUTB
O
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked
out on the falling edge of the ADSCLK input and 14 ADSCLKs are required to access the data. The data
simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream
consists of two leading zeros followed by the 12 bits of conversion data. The data is provided MSB first.
If CS is held low for 16 ADSCLK cycles rather than 14, then two trailing zeros will appear after the 12 bits
of data. If CS is held low for a further 16 ADSCLK cycles on either DOUTA or DOUTB, the data from the other
ADC follows on the DOUT pin. This allows data from a simultaneous conversion on both ADCs to be
gathered in serial format on either DOUTA or DOUTB using only one serial port. For more information, see
the ADC鈥擲erial Interface section.
VDRIVE
P
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the digital I/O
interface operates. This pin should be decoupled to DGND. The voltage at this pin may be different than
that at AVDD and DVDD but should never exceed either by more than 0.3 V.
DVDD
P
Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the internal
ADC. The DVDD and AVDD voltages should ideally be at the same potential and must not be more than
0.3 V apart even on a transient basis. This supply should be decoupled to DGND.
Table 12. ADC鈥擲ignal Descriptions (ADSP-BF506F Processor Only) (Continued)
Signal Name
Type Function
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| GMC60DREH-S734 | CONN EDGECARD 120PS .100 EYELET |
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| HMC05DRXH | CONN EDGECARD 10POS DIP .100 SLD |
| RGM43DRSD-S288 | CONN EDGECARD 86POS .156 EXTEND |
| VE-B5K-CY-F1 | CONVERTER MOD DC/DC 40V 50W |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ADSP-BF506BSWZ-4FX | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:- Trays |
| ADSP-BF506F | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:LOW POWER BLACKFIN WITH ADVANCED EMBEDDED CONNECTIVITY - Bulk |
| ADSPBF506FBSWZ-ENG | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:- Trays |
| ADSP-BF506KSWZ-3F | 鍔熻兘鎻忚堪:IC DSP 12BIT 300MHZ 120LQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - DSP锛堟暩(sh霉)瀛楀紡淇¤櫉铏曠悊鍣級 绯诲垪:Blackfin® 妯�(bi膩o)婧�(zh菙n)鍖呰:2 绯诲垪:StarCore 椤炲瀷:SC140 鍏�(n猫i)鏍� 鎺ュ彛:DSI锛屼互澶恫(w菐ng)锛孯S-232 鏅傞悩閫熺巼:400MHz 闈炴槗澶卞収(n猫i)瀛�:澶栭儴 鑺墖涓奟AM:1.436MB 闆诲 - 杓稿叆/杓稿嚭:3.30V 闆诲 - 鏍稿績:1.20V 宸ヤ綔婧害:-40°C ~ 105°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:431-BFBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:431-FCPBGA锛�20x20锛� 鍖呰:鎵樼洡 |
| ADSP-BF506KSWZ-4F | 鍔熻兘鎻忚堪:IC DSP 12BIT 400MHZ 120LQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - DSP锛堟暩(sh霉)瀛楀紡淇¤櫉铏曠悊鍣級 绯诲垪:Blackfin® 妯�(bi膩o)婧�(zh菙n)鍖呰:2 绯诲垪:StarCore 椤炲瀷:SC140 鍏�(n猫i)鏍� 鎺ュ彛:DSI锛屼互澶恫(w菐ng)锛孯S-232 鏅傞悩閫熺巼:400MHz 闈炴槗澶卞収(n猫i)瀛�:澶栭儴 鑺墖涓奟AM:1.436MB 闆诲 - 杓稿叆/杓稿嚭:3.30V 闆诲 - 鏍稿績:1.20V 宸ヤ綔婧害:-40°C ~ 105°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:431-BFBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:431-FCPBGA锛�20x20锛� 鍖呰:鎵樼洡 |
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