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參數(shù)資料
| 型號： | ADSP-2196MKSTZ-160 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 50/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 144-LQFP |
| 標準包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，SPI，SSP，UART |
| 時鐘速率： | 160MHz |
| 非易失內(nèi)存： | ROM（48 kB） |
| 芯片上RAM： | 40kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
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This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
54
REV. PrA
For current information contact Analog Devices at 800/262-5643
ADSP-2196
September 2001
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The P
EXT equation is calculated for each class of pins that
can drive as shown in Table 24.
A typical power consumption can now be calculated for
these conditions by adding a typical internal power dissipa-
tion with the formula in Figure 30.
Where:
P
EXT is from Table 24
P
INT is IDDINT
2.5V, using the calculation I
DDINT listed in
Note that the conditions causing a worst-case P
EXT are
different from those causing a worst-case P
INT. Maximum
P
INT cannot occur while 100% of the output pins are
switching from all ones to all zeros. Note also that it is not
common for an application to have 100% or even 50% of
the outputs switching simultaneously.
Test Conditions
The DSP is tested for output enable, disable, and hold time.
Output Disable Time
Output pins are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay
from their output high or low voltage. The time for the
voltage on the bus to decay by – V is dependent on the
capacitive load, C
L and the load current, IL. This decay time
can be approximated by the equation in Figure 31.
The output disable time t
DIS is the difference between
t
t
MEASURED is the interval from when the reference signal
switches to when the output voltage decays –V from the
measured output high or output low voltage. The t
DECAY is
calculated with test loads C
L and IL, and with –V equal to
0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have
made a transition from a high impedance state to when they
start driving. The output enable time t
ENA is the interval
from when a reference signal reaches a high or low voltage
level to when the output has reached a specified high or low
trip point, as shown in the Output Enable/Disable diagram
(Figure 32). If multiple pins (such as the data bus) are
enabled, the measurement value is that of the first pin to
start driving.
Table 24. PEXT Calculation
Pin Type
# of Pins
% Switching
C
f
VDD
2
= PEXT
Address
15
50
TBD pF
25.0 MHz
10.9 V
=TBD W
MSx
10
TBD pF
25.0 MHz
10.9 V
=TBD W
WR
1—
TBD pF
25 MHz
10.9 V
=TBD W
Data
16
50
TBD pF
25.0 MHz
10.9 V
=TBD W
CLKOUT
1
—
TBD pF
100 MHz
10.9 V
=TBD W
P
EXT =TBD W
Figure 30. PTOTAL (Typical) Calculation
Figure 31. Decay Time Calculation
P
TOTAL
P
=
EXT
P
INT
+
t
DECAY
C
L V
I
L
---------------
=
Figure 32. Output Enable/Disable
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