參數(shù)資料
型號(hào): ADSP-2196MKSTZ-160
廠商: Analog Devices Inc
文件頁(yè)數(shù): 14/68頁(yè)
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 144-LQFP
標(biāo)準(zhǔn)包裝: 1
系列: ADSP-21xx
類型: 定點(diǎn)
接口: 主機(jī)接口,SPI,SSP,UART
時(shí)鐘速率: 160MHz
非易失內(nèi)存: ROM(48 kB)
芯片上RAM: 40kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 2.50V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
35(/,0,1$5< 7(&+1,&$/ '$7$
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
21
REV. PrA
For current information contact Analog Devices at 800/262-5643
ADSP-2196
September 2001
RCLK1–0
I/O/T
SPORT1–0 Receive Clock
RCLK2/SCK1
I/O/T
SPORT2 Receive Clock/SPI1 Serial Clock
RFS1–0
I/O/T
SPORT1–0 Receive Frame Sync
RFS2/MOSI1
I/O/T
SPORT2 Receive Frame Sync/SPI1 Master-Output, Slave-Input data
TCLK1–0
I/O/T
SPORT1–0 Transmit Clock
TCLK2/SCK0
I/O/T
SPORT2 Transmit Clock/SPI0 Serial Clock
TFS1–0
I/O/T
SPORT1–0 Transmit Frame Sync
TFS2/MOSI0
I/O/T
SPORT2 Transmit Frame Sync/SPI0 Master-Output, Slave-Input data
DR1–0
I/T
SPORT1–0 Serial Data Receive
DR2/MISO1
I/O/T
SPORT2 Serial Data Receive/SPI1 Master-Input, Slave-Output data
DT1–0
O/T
SPORT1–0 Serial Data Transmit
DT2/MISO0
I/O/T
SPORT2 Serial Data Transmit/SPI0 Master-Input, Slave-Output data
TMR2–0
I/O/T
Timer output or capture
RXD
I
UART Serial Receive Data
TXD
O
UART Serial Transmit Data
RESET
I
Processor Reset. Resets the ADSP-2196 to a known state and begins execution at the program
memory location specified by the hardware reset vector address. The RESET input must be
asserted (low) at power-up. The RESET pin has a 85 k
internal pull-up resistor.
TCK
I
Test Clock (JTAG). Provides a clock for JTAG boundary scan. The TCK pin has a 85 k
internal pull-up resistor.
TMS
I
Test Mode Select (JTAG). Used to control the test state machine. The TMS pin has a 85 k
internal pull-up resistor.
TDI
I
Test Data Input (JTAG). Provides serial data for the boundary scan logic. The TDI pin has
a 85 k
internal pull-up resistor.
TDO
O
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST
I
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after
power-up or held low for proper operation of the ADSP-2196. The TRST pin has a 65 k
internal pull-down resistor.
EMU
O
Emulation Status (JTAG). Must be connected to the ADSP-2196 emulator target board
connector only.
V
DDINT
P
Core Power Supply. Nominally 2.5 V dc and supplies the DSP’s core processor. (four pins).
V
DDEXT
P
I/O Power Supply; Nominally 3.3 V dc. (nine pins).
GND
G
Power Supply Return. (twelve pins).
NC
Do Not Connect. Reserved pins that must be left open and unconnected.
Table 7. Pin Descriptions (Continued)
Pin
Type
Function
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