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參數資料
| 型號： | ADSP-2196MKSTZ-160 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 10/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 144-LQFP |
| 標準包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，SPI，SSP，UART |
| 時鐘速率： | 160MHz |
| 非易失內存： | ROM（48 kB） |
| 芯片上RAM： | 40kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
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For current information contact Analog Devices at 800/262-5643
ADSP-2196
September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
18
REV. PrA
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As can be seen in Figure 7, there are two sets of signals on
the header. There are the standard JTAG signals TMS,
TCK, TDI, TDO, TRST, and EMU used for emulation
purposes (via an emulator). There are also secondary JTAG
signals BTMS, BTCK, BTDI, and BTRST that are option-
ally used for board-level (boundary scan) testing.
When the emulator is not connected to this header, place
jumpers across BTMS, BTCK, BTRST, and BTDI as
shown in Figure 8. This holds the JTAG signals in the
correct state to allow the DSP to run free. Remove all the
jumpers when connecting the emulator to the JTAG header.
JTAG Emulator Pod Connector
Figure 9 details the dimensions of the JTAG pod connector
at the 14-pin target end. Figure 10 displays the keep-out
area for a target board header. The keep-out area allows the
pod connector to properly seat onto the target board header.
This board area should contain no components (chips,
resistors, capacitors, etc.). The dimensions are referenced
to the center of the 0.25" square post pin.
Design-for-Emulation Circuit Information
For details on target board design issues including: single
processor connections, multiprocessor scan chains, signal
buffering, signal termination, and emulator pod logic, see
the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.ana-
log.com)—use site search on “EE-68”. This document is
updated regularly to keep pace with improvements to
emulator support.
Additional Information
This data sheet provides a general overview of the
ADSP-2196 architecture and functionality. For detailed
information on the ADSP-219x family core architecture
and instruction set, refer to the ADSP-219x/2191 DSP
Hardware Reference.
PIN DESCRIPTIONS
ADSP-2196 pin definitions are listed in Table 7. All
ADSP-2196 inputs are asynchronous and can be asserted
asynchronously to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to V
DDEXT or GND,
except for ADDR21–0, DATA15–0, PF7-0, and inputs that
have internal pull-up or pull-down resistors (TRST,
BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS,
TDI, and RESET)—these pins can be left floating. These
pins have a logic-level hold circuit that prevents input from
floating internally.
The following symbols appear in the Type column of
Table 7: G = Ground, I = Input, O = Output, P = Power
Supply, and T = Three-State.
Figure 8. JTAG Target Board Connector with No Local
Boundary Scan
Figure 9. JTAG Pod Connector Dimensions
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(0 8
*1'
70 6
7&.
7567
7',
7'2
*1'
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*1'
Figure 10. JTAG Pod Connector Keep-Out Area
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