參數(shù)資料
型號(hào)： ADSP-21160MKB-80
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 51/52頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 32BIT 400 BGA
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類(lèi)型： 浮點(diǎn)
接口： 主機(jī)接口，連接端口，串行端口
時(shí)鐘速率： 80MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 2.50V
工作溫度： 0°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 400-BBGA
供應(yīng)商設(shè)備封裝： 400-PBGA（27x27）
包裝： 托盤(pán)
ADSP-21160M
–8–
REV. 0
Also, the clearance (length, width, and height) around the
header must be considered. Leave a clearance of at least
0.15" and 0.10" around the length and width of the header,
and reserve a height clearance to attach and detach the pod
connector.
As can be seen in Figure 6, there are two sets of signals on
the header. There are the standard JTAG signals TMS,
TCK, TDI, TDO, TRST, and EMU used for emulation
purposes (via an emulator). There are also secondary JTAG
signals BTMS, BTCK, BTDI, and BTRST that are option-
ally used for board-level (boundary scan) testing.
When the emulator is not connected to this header, place
jumpers across BTMS, BTCK, BTRST, and BTDI as
shown in Figure 7. This holds the JTAG signals in the
correct state to allow the DSP to run free. Remove all the
jumpers when connecting the emulator to the JTAG header.
JTAG Emulator Pod Connector
Figure 8 details the dimensions of the JTAG pod connector
at the 14-pin target end. Figure 9 displays the keep-out area
for a target board header. The keep-out area allows the pod
connector to properly seat onto the target board header.
This board area should contain no components (chips,
resistors, capacitors, etc.). The dimensions are referenced
to the center of the 0.25" square post pin.
Design-for-Emulation Circuit Information
For details on target board design issues including: single
processor connections, multiprocessor scan chains, signal
buffering, signal termination, and emulator pod logic, see
the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website—use site search on
“EE-68” (www.analog.com). This document is updated
regularly to keep pace with improvements to emulator
support.
Additional Information
This data sheet provides a general overview of the
ADSP-21160M architecture and functionality. For detailed
information on the ADSP-2116x Family core architecture
and instruction set, refer to the ADSP-2116x SHARC DSP
Hardware Reference.
PIN FUNCTION DESCRIPTIONS
ADSP-21160M pin definitions are listed below. Inputs
identified as synchronous (S) must meet timing require-
ments with respect to CLKIN (or with respect to TCK for
TMS, TDI). Inputs identified as asynchronous (A) can be
asserted asynchronously to CLKIN (or to TCK for TRST).
Figure 6. JTAG Target Board Connector for JTAG
Equipped Analog Devices DSP (Jumpers in Place)
Figure 9. JTAG Pod Connector Keep-Out Area
723 9,(:
(0 8
*1'
70 6
7&.
7567
7',
7'2
*1'
.(< 12 3,1
%70 6
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*1'
Figure 7. JTAG Target Board Connector with No Local
Boundary Scan
Figure 8. JTAG Pod Connector Dimensions
723 9,(:
(0 8
*1'
70 6
7&.
7567
7',
7'2
*1'
.(< 12 3,1
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*1'
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