參數(shù)資料
型號： ADE7878ACPZ-RL
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind
中文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40
文件頁數(shù)： 86/96頁
文件大?。?/td> 1096K
代理商： ADE7878ACPZ-RL
ADE7854/ADE7858/ADE7868/ADE7878
Rev. E| Page 87 of 96
Table 45. CFMODE Register (Address 0xE610)
Bit
Location
Bit Mnemonic
Default Value
Description
000: the CF1 frequency is proportional to the sum of total active powers on each phase
identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register.
001: the CF1 frequency is proportional to the sum of total reactive powers on each phase
identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register. This condition does not
have any consequence for the ADE7854.
010: the CF1 frequency is proportional to the sum of apparent powers on each phase
identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register.
011: the CF1 frequency is proportional to the sum of fundamental active powers on each
phase identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register. This condition does
not have any consequence for the ADE7854, ADE7858, and ADE7868.
100: the CF1 frequency is proportional to the sum of fundamental reactive powers on each
phase identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register. This condition does
not have any consequence for the ADE7854, ADE7858, and ADE7868.
2:0
CF1SEL[2:0]
000
101, 110, 111: reserved. When set, the CF1 signal is not generated.
000: the CF2 frequency is proportional to the sum of total active powers on each phase
identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register.
001: the CF2 frequency is proportional to the sum of total reactive powers on each phase
identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register. This condition does not
have any consequence for the ADE7854.
010: the CF2 frequency is proportional to the sum of apparent powers on each phase
identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register.
011: the CF2 frequency is proportional to the sum of fundamental active powers on each
phase identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register. This condition does
not have any consequence for the ADE7854, ADE7858, and ADE7868.
100: the CF2 frequency is proportional to the sum of fundamental reactive powers on each
phase identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register. This condition does
not have any consequence for the ADE7854, ADE7858, and ADE7868.
5:3
CF2SEL[2:0]
001
101,110,111: reserved. When set, the CF2 signal is not generated.
000: the CF3 frequency is proportional to the sum of total active powers on each phase
identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register.
001: the CF3 frequency is proportional to the sum of total reactive powers on each phase
identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register. This condition does not
have any consequence for the ADE7854.
010: the CF3 frequency is proportional to the sum of apparent powers on each phase
identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register.
011: CF3 frequency is proportional to the sum of fundamental active powers on each phase
identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register. This condition does not
have any consequence for the ADE7854, ADE7858, and ADE7868.
100: CF3 frequency is proportional to the sum of fundamental reactive powers on each
phase identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register. This condition does
not have any consequence for the ADE7854, ADE7858, and ADE7868.
8:6
CF3SEL[2:0]
010
101,110,111: reserved. When set, the CF3 signal is not generated.
9
CF1DIS
1
When this bit is set to 1, the CF1 output is disabled. The respective digital to frequency
converter remains enabled even if CF1DIS = 1.
When this bit is set to 0, the CF1 output is enabled.
10
CF2DIS
1
When this bit is set to 1, the CF2 output is disabled. The respective digital to frequency
converter remains enabled even if CF2DIS = 1.
When this bit is set to 0, the CF2 output is enabled.
11
CF3DIS
1
When this bit is set to 1, the CF3 output is disabled. The respective digital to frequency
converter remains enabled even if CF3DIS = 1.
When this bit is set to 0, the CF3 output is enabled.
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