參數(shù)資料
型號： ADE7878ACPZ-RL
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind
中文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40
文件頁數(shù)： 83/96頁
文件大小： 1096K
代理商： ADE7878ACPZ-RL
ADE7854/ADE7858/ADE7868/ADE7878
Rev. E| Page 84 of 96
Bit
Location
Bit Mnemonic
Default Value
Description
5
ZXTOVC
0
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C voltage is
missing.
6
ZXTOIA
0
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A current is
missing.
7
ZXTOIB
0
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B current is
missing.
8
ZXTOIC
0
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C current is
missing.
9
ZXVA
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase A
voltage.
10
ZXVB
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase B
voltage.
11
ZXVC
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase C
voltage.
12
ZXIA
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase A
current.
13
ZXIB
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase B
current.
14
ZXIC
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase C
current.
15
RSTDONE
0
Because the RSTDONE interrupt cannot be disabled, this bit does not have any functionality
attached. It can be set to 1 or cleared to 0 without having any effect.
16
SAG
0
When this bit is set to 1, it enables an interrupt when a SAG event occurs on one of the
phases indicated by Bits[14:12] (VSPHASE[x]) in the PHSTATUS register (see Table 41).
17
OI
0
When this bit is set to 1, it enables an interrupt when an overcurrent event occurs on one of
the phases indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register (see Table 41).
18
OV
0
When this bit is set to 1, it enables an interrupt when an overvoltage event occurs on one of
the phases indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register (see Table 41).
19
SEQERR
0
When this bit is set to 1, it enables an interrupt when a negative-to-positive zero crossing on
Phase A voltage is not followed by a negative-to-positive zero crossing on Phase B voltage,
but by a negative-to-positive zero crossing on Phase C voltage.
20
MISMTCH
0
When this bit is set to 1, it enables an interrupt when
ISUMLVL
INWV
ISUM
>
is
greater than the value indicated in ISUMLVL register. Setting this bit to1 does not have any
consequence for ADE7854 and ADE7858.
22:21
Reserved
00
Reserved. These bits do not manage any functionality.
23
PKI
0
When this bit is set to 1, it enables an interrupt when the period used to detect the peak
value in the current channel has ended.
24
PKV
0
When this bit is set to 1, it enables an interrupt when the period used to detect the peak
value in the voltage channel has ended.
31:25
Reserved
000 0000
Reserved. These bits do not manage any functionality.
Table 41. PHSTATUS Register (Address 0xE600)
Bit
Location
Bit Mnemonic
Default Value
Description
2:0
Reserved
000
Reserved. These bits are always 0.
3
OIPHASE[0]
0
When this bit is set to 1, Phase A current generates Bit 17 (OI) in the STATUS1 register.
4
OIPHASE[1]
0
When this bit is set to 1, Phase B current generates Bit 17 (OI) in the STATUS1 register.
5
OIPHASE[2]
0
When this bit is set to 1, Phase C current generates Bit 17 (OI) in the STATUS1 register.
8:6
Reserved
000
Reserved. These bits are always 0.
9
OVPHASE[0]
0
When this bit is set to 1, Phase A voltage generates Bit 18 (OV) in the STATUS1 register.
10
OVPHASE[1]
0
When this bit is set to 1, Phase B voltage generates Bit 18 (OV) in the STATUS1 register.
11
OVPHASE[2]
0
When this bit is set to 1, Phase C voltage generates Bit 18 (OV) in the STATUS1 register.
12
VSPHASE[0]
0
When this bit is set to 1, Phase A voltage generates Bit 16 (SAG) in the STATUS1 register.
13
VSPHASE[1]
0
When this bit is set to 1, Phase B voltage generates Bit 16 (SAG) in the STATUS1 register.
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