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參數(shù)資料
| 型號： | ADE7878ACPZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40 |
| 文件頁數(shù)： | 29/96頁 |
| 文件大?。?/td> | 1096K |
| 代理商： | ADE7878ACPZ-RL |
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ADE7854/ADE7858/ADE7868/ADE7878
Rev. E | Page 35 of 96
MASK1 is set, the IRQ1 interrupt pin is driven low in case of a
SAG event in the same moment the Status Bit 16 (SAG) in
STATUS1 register is set to 1. The SAG status bit in the STATUS1
register and all Bits[14:12] (VSPHASE[2], VSPHASE[1], and
VSPHASE[0]]) of the PHSTATUS register are cleared, and the
IRQ1 pin is returned to high by writing to the STATUS1
register with the status bit set to 1.
When the Phase B voltage falls below the indicated threshold
into the SAGLVL register for two line cycles, Bit VSPHASE[1]
in the PHSTATUS register is set to 1, and Bit VSPHASE[0] is
cleared to 0. Simultaneously, Bit 16 (SAG) in the STATUS1 register
is set to 1 to indicate the condition.
Note that the internal zero-crossing counter is always active. By
setting the SAGLVL register, the first SAG detection result is,
therefore, not executed across a full SAGCYC period. Writing to
the SAGCYC register when the SAGLVL register is already initia-
lized resets the zero-crossing counter, thus ensuring that the first
SAG detection result is obtained across a full SAGCYC period.
The recommended procedure to manage SAG events is the
following:
1.
Enable SAG interrupts in the MASK1 register by setting
Bit 16 (SAG) to 1.
2.
When a SAG event happens, the IRQ1 interrupt pin goes
low and Bit 16 (SAG) in the STATUS1 is set to 1.
3.
The STATUS1 register is read with Bit 16 (SAG) set to 1.
4.
The PHSTATUS register is read, identifying on which
phase or phases a SAG event happened.
5.
The STATUS1 register is written with Bit 16 (SAG) set to 1.
Immediately, the SAG bit and all Bits[14:12] (VSPHASE[2],
VSPHASE[1], and VSPHASE[0]) of the PHSTATUS register
are erased.
SAG Level Set
The content of the SAGLVL[23:0] SAG level register is compared
to the absolute value of the output from HPF. Writing 5,928,256
(0x5A7540) to the SAGLVL register, puts the SAG detection
level at full scale (see the Voltage Channel ADC section), thus;
the SAG event is triggered continuously. Writing 0x00 or 0x01
puts the SAG detection level at 0, therefore, the SAG event is
never triggered.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE78xx work on 32-, 16-, or 8-bit words.
Similar to the register presented in Figure 34, the SAGLVL
register is accessed as a 32-bit register with eight MSBs padded
with 0s.
Peak Detection
The ADE7854/ADE7858/ADE7868/ADE7878 record the
maximum absolute values reached by the voltage and current
channels over a certain number of half-line cycles and stores
them into the less significant 24 bits of the VPEAK and IPEAK
32-bit registers.
The PEAKCYC register contains the number of half-line cycles
used as a time base for the measurement. The circuit uses the
zero-crossing points identified by the zero-crossing detection
circuit. Bits[4:2] (PEAKSEL[2:0]) in the MMODE register select
the phases upon which the peak measurement is performed. Bit 2
selects Phase A, Bit 3 selects Phase B, and Bit 4 selects Phase C.
Selecting more than one phase to monitor the peak values
decreases proportionally the measurement period indicated in
the PEAKCYC register because zero crossings from more
phases are involved in the process. When a new peak value is
determined, one of Bits[26:24] (IPPHASE[2:0] or VPPHASE[2:0])
in the IPEAK and VPEAK registers is set to 1, identifying the
phase that triggered the peak detection event. For example, if a
peak value has been identified on Phase A current, Bit 24
(IPPHASE[0]) in the IPEAK register is set to 1. If next time a
new peak value is measured on Phase B, Bit 24 (IPPHASE[0])
of the IPEAK register is cleared to 0, and Bit 25 (IPPHASE[1])
of the IPEAK register is set to 1. Figure 48 shows the composition
of the IPEAK and VPEAK registers.
PEAK DETECTED
ON PHASE C
00000
31
27 26 25 24 23
0
24 BIT UNSIGNED NUMBER
PEAK DETECTED
ON PHASE A
IPPHASE/VPPHASE BITS
PEAK DETECTED
ON PHASE B
0
85
10
-0
34
Figure 48. Composition of IPEAK[31:0] and VPEAK[31:0] Registers
PHASE A
CURRENT
PHASE B
CURRENT
BIT 24
OF IPEAK
BIT 25
OF IPEAK
PEAK VALUE WRITTEN INTO
IPEAK AT THE END OF FIRST
PEAKCYC PERIOD
END OF FIRST
PEAKCYC = 16 PERIOD
BIT 24 OF IPEAK
CLEARED TO 0 AT
THE END OF SECOND
PEAKCYC PERIOD
BIT 25 OF IPEAK
SET TO 1 AT THE
END OF SECOND
PEAKCYC PERIOD
END OF SECOND
PEAKCYC = 16 PERIOD
PEAK VALUE WRITTEN INTO
IPEAK AT THE END OF SECOND
PEAKCYC PERIOD
08
51
0-
0
35
Figure 49. Peak Level Detection
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