- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223308 > ADE7878ACPZ-RL (ANALOG DEVICES INC) Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind PDF資料下載
參數(shù)資料
| 型號： | ADE7878ACPZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40 |
| 文件頁數(shù)： | 52/96頁 |
| 文件大?。?/td> | 1096K |
| 代理商： | ADE7878ACPZ-RL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁當前第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁
ADE7854/ADE7858/ADE7868/ADE7878
Rev. E | Page 56 of 96
In the ADE7854/ADE7858/ADE7868/ADE7878, the phase
apparent powers are accumulated in the AVAHR, BVAHR, and
CVAHR 32-bit signed registers. The apparent energy register
content can roll over to full-scale negative (0x80000000) and
continue increasing in value when the apparent power is posi-
tive. Conversely, if because of offset compensation in the rms
datapath, the apparent power is negative, the energy register
underflows to full-scale positive (0x7FFFFFFF) and continues
to decrease in value.
The maximum value that can be stored in the xVAHR
accumulation register before it overflows is 231 1 or
0x7FFFFFFF. The integration time is calculated as
Time = 0x7FFF,FFFF × 125 μs = 74 hr 33 min 55 sec
(45)
Energy Accumulation Mode
The apparent power accumulated in each accumulation register
depends on the configuration of Bits[5:4] (CONSEL[1:0]) in the
ACCMODE register. The various configurations are described
in Table 20.
Bit 4 (VAEHF) in the STATUS0 register is set when Bit 30 of one of
the xVAHR registers changes, signifying one of these registers is
half full. As the apparent power is always positive and the xVAHR
registers are signed, the VA-hour registers become half full when
they increment from 0x3FFFFFFF to 0x4000 0000. Interrupts
attached to Bit VAEHF in the STATUS0 register can be enabled by
setting Bit 4 in the MASK0 register. If enabled, the IRQ0 pin is set
low and the status bit is set to 1 whenever one of the Energy
Registers xVAHR becomes half full. The status bit is cleared and
the IRQ0 pin is set to high by writing to the STATUS0 register
with the corresponding bit set to 1.
Table 20. Inputs to VA-Hour Accumulation Registers
CONSEL[1:0]
AVAHR
BVAHR
CVAHR
00
AVRMS × AIRMS
BVRMS × BIRMS
CVRMS × CIRMS
01
AVRMS × AIRMS
0
CVRMS × CIRMS
10
AVRMS × AIRMS
BVRMS × BIRMS
CVRMS × CIRMS
VB = VA VC
11
AVRMS × AIRMS
BVRMS × BIRMS
CVRMS × CIRMS
VB = VA
Line Cycle Apparent Energy Accumulation Mode
As described in the Line Cycle Active Energy Accumulation
Mode section, in line cycle energy accumulation mode, the
energy accumulation can be synchronized to the voltage channel
zero crossings allowing apparent energy to be accumulated over an
integral number of half line cycles. In this mode, the ADE7854/
ADE7858/ADE7868/ADE7878 transfer the apparent energy
accumulated in the 32-bit internal accumulation registers into
the xVAHR registers after an integral number of line cycles, as
shown in Figure 69. The number of half line cycles is specified
in the LINECYC register.
Setting Bit 6 (RSTREAD) of the LCYCMODE register enables
a read-with-reset for all xVAHR accumulation registers, that is,
the registers are reset to 0 after a read operation.
Integration Time Under Steady Load
The discrete time sample period for the accumulation register is
125 μs (8 kHz frequency). With full-scale pure sinusoidal signals
on the analog inputs, the average word value representing the
apparent power is PMAX. If the VATHR threshold register is set
at the PMAX level, this means the DSP generates a pulse that
is added at the xVAHR registers every 125 μs.
ZERO-
CROSSING
DETECTION
(PHASE A)
ZERO-
CROSSING
DETECTION
(PHASE B)
CALIBRATION
CONTROL
ZERO-
CROSSING
DETECTION
(PHASE C)
LINECYC[15:0]
AVAHR[31:0]
ZXSEL[0] IN
LCYCMODE[7:0]
ZXSEL[1] IN
LCYCMODE[7:0]
ZXSEL[2] IN
LCYCMODE[7:0]
AVAGAIN
AIRMS
AVRMS
ACCUMULATOR
VAHR[47:0]
32-BIT
REGISTER
08
51
0-
0
49
Figure 69. Line Cycle Apparent Energy Accumulation Mode
相關PDF資料 |
PDF描述 |
|---|---|
| ADG529FTQ | 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, CDIP18 |
| ADJ24006 | POWER/SIGNAL RELAY, SPST, LATCHED, 0.042A (COIL), 6VDC (COIL), 250mW (COIL), THROUGH HOLE-STRAIGHT MOUNT |
| ADJ24012 | POWER/SIGNAL RELAY, SPST, LATCHED, 0.021A (COIL), 12VDC (COIL), 250mW (COIL), THROUGH HOLE-STRAIGHT MOUNT |
| ADJ24024 | POWER/SIGNAL RELAY, SPST, LATCHED, 0.01A (COIL), 24VDC (COIL), 250mW (COIL), THROUGH HOLE-STRAIGHT MOUNT |
| ADJ24048 | POWER/SIGNAL RELAY, SPST, LATCHED, 0.005A (COIL), 48VDC (COIL), 250mW (COIL), THROUGH HOLE-STRAIGHT MOUNT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADE7878XCPZ | 制造商:Analog Devices 功能描述:POLY PHASE MULTIFUNCTION ENERGY METERING IC WITH TOTAL - Bulk |
| ADE7880 | 制造商:Analog Devices 功能描述:BOARD EVAL ENERGY METER ADE |
| ADE7880ACPZ | 功能描述:IC ENERGY METERING 3PH 40LFCSP RoHS:是 類別:集成電路 (IC) >> PMIC - 能量測量 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:* |
| ADE7880ACPZ-RL | 功能描述:IC ENERGY METERING 3PH 40LFCSP RoHS:是 類別:集成電路 (IC) >> PMIC - 能量測量 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:* |
| ADE7903ARWZ | 功能描述:Energy Monitor (Power Meter) 24 bit SPI 20-SOIC 制造商:analog devices inc. 系列:- 包裝:管件 零件狀態(tài):有效 類型:能量監(jiān)測器（功率計） 分辨率（位）:24 b 采樣率（每秒）:- 數(shù)據(jù)接口:SPI 電壓源:單電源 電壓 - 電源:2.97 V ~ 3.63 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 供應商器件封裝:20-SOIC 標準包裝:37 |
發(fā)布緊急采購，3分鐘左右您將得到回復。