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參數(shù)資料
| 型號(hào)： | ADE7878ACPZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40 |
| 文件頁數(shù)： | 8/96頁 |
| 文件大小： | 1096K |
| 代理商： | ADE7878ACPZ-RL |
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ADE7854/ADE7858/ADE7868/ADE7878
Rev. E | Page 16 of 96
Pin No.
Mnemonic
Description
18, 19, 22, 23
VN, VCP, VBP, VAP
Analog Inputs for the Voltage Channel. This channel is used with the voltage transducer and is
referenced as the voltage channel in this document. These inputs are single-ended voltage inputs
with a maximum signal level of ±0.5 V with respect to VN for specified operation. This channel also
has an internal PGA.
24
AVDD
This pin provides access to the on-chip 2.5 V analog low dropout regulator (LDO). Do not connect
external active circuitry to this pin. Decouple this pin with a 4.7 μF capacitor in parallel with a
ceramic 220 nF capacitor.
25
AGND
Ground Reference. This pin provides the ground reference for the analog circuitry. Tie this pin to the
analog ground plane or to the quietest ground reference in the system. Use this quiet ground
reference for all analog circuitry, for example, antialiasing filters, current, and voltage transducers.
26
VDD
Supply Voltage. This pin provides the supply voltage. In PSM0 (normal power mode), maintain the
supply voltage at 3.3 V ± 10% for specified operation. In PSM1 (reduced power mode), PSM2 (low
power mode), and PSM3 (sleep mode), when the ADE7868/ADE7878 is supplied from a battery,
maintain the supply voltage between 2.4 V and 3.7 V. Decouple this pin to AGND with a 10 μF
capacitor in parallel with a ceramic 100 nF capacitor. The only modes available on the ADE7858 and
ADE7854 are the PSM0 and PSM3 power modes.
27
CLKIN
Master Clock. An external clock can be provided at this logic input. Alternatively, a parallel resonant
AT-cut crystal can be connected across CLKIN and CLKOUT to provide a clock source for the
ADE7854/ADE7858/ADE7868/ADE7878. The clock frequency for specified operation is 16.384 MHz.
Use ceramic load capacitors of a few tens of picofarad with the gate oscillator circuit. Refer to the
crystal manufacturer’s data sheet for load capacitance requirements.
28
CLKOUT
A crystal can be connected across this pin and CLKIN (as previously described with Pin 27 in this
table) to provide a clock source for the ADE7854/ADE7858/ADE7868/ADE7878. The CLKOUT pin can
drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used.
29, 32
IRQ0, IRQ1
Interrupt Request Outputs. These are active low logic outputs. See the Interrupts section for a
detailed presentation of the events that can trigger interrupts.
33, 34, 35
CF1, CF2,
CF3/HSCLK
Calibration Frequency (CF) Logic Outputs. These outputs provide power information based on the
CF1SEL[2:0], CF2SEL[2:0], and CF3SEL[2:0] bits in the CFMODE register. These outputs are used for
operational and calibration purposes. The full-scale output frequency can be scaled by writing to the
CF1DEN, CF2DEN, and CF3DEN registers, respectively (see the Energy-to-Frequency Conversion
section). CF3 is multiplexed with the serial clock output of the HSDC port.
36
SCLK/SCL
Serial Clock Input for SPI Port/Serial Clock Input for I2C Port. All serial data transfers are synchronized
to this clock (see the Serial Interfaces section). This pin has a Schmidt trigger input for use with a
clock source that has a slow edge transition time, for example, opto-isolator outputs.
37
MISO/HSD
Data Out for SPI Port/Data Out for HSDC Port.
38
MOSI/SDA
Data In for SPI Port/Data Out for I2C Port.
39
SS/HSA
Slave Select for SPI Port/HSDC Port Active.
EP
Exposed Pad
Create a similar pad on the PCB under the exposed pad. Solder the exposed pad to the pad on the
PCB to confer mechanical strength to the package. Do not connect the pads to AGND.
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