參數(shù)資料
型號: AD9910BSVZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 8/64頁
文件大?。?/td> 0K
描述: IC DDS 1GSPS 14BIT PAR 100TQFP
產(chǎn)品培訓模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設計資源: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
標準包裝: 1,000
分辨率(位): 14 b
主 fclk: 1GHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應商設備封裝: 100-TQFP-EP(14x14)
包裝: 帶卷 (TR)
AD9910
Data Sheet
Rev. D | Page 16 of 64
APPLICATION CIRCUITS
LOOP
FILTER
PHASE
COMPARATOR
VCO
AD9910
REF_CLK
REFERENCE
CHARGE
PUMP
AD9510, AD9511, ADF4106
÷
06479-
056
LPF
Figure 19. DDS in PLL Feedback Locking to Reference, Offering Fine Frequency and Delay Adjust Tuning
AD9910
(SLAVE 1)
AD9910
(MASTER)
CLOCK
SOURCE
AD9910
(SLAVE 2)
AD9910
(SLAVE 3)
FPGA
DATA
SYNC_CLK
REF_CLK
SYNC_CLK
FPGA
DATA
FPGA
DATA
FPGA
SYNC_CLK
C1
S1
C2
S2
C3
S3
C4
S4
A1
A2
A4
A3
A_END
CENTRAL
CONTROL
AD9510
CLOCK DISTRIBUTOR
WITH
DELAY EQUALIZATION
SYNC_OUT
AD9510
SYNCHRONIZATION
DELAY EQUALIZATION
06479-
058
Figure 20. Synchronizing Multiple Devices to Increase Channel Capacity Using the AD9510 as a Clock Distributor for the Reference and Synchronization Clock
AD9910
REFCLK
n
PROGRAMMABLE 1 TO 32
DIVIDER AND DELAY ADJUST
CLOCK OUTPUT
SELECTION(S)
n = DEPENDENT ON PRODUCT SELECTION.
AD9515
AD9514
AD9513
AD9512
LVPECL
LVDS
CMOS
CH 2
06479-
057
LPF
Figure 21. Clock Generation Circuit Using the AD9512/AD9513/AD9514/AD9515 Series of Clock Distribution Chips
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