參數(shù)資料
型號： AD9910BSVZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 15/64頁
文件大?。?/td> 0K
描述： IC DDS 1GSPS 14BIT PAR 100TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
標(biāo)準(zhǔn)包裝： 1,000
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
AD9910
Data Sheet
Rev. D | Page 22 of 64
MODE PRIORITY
The three different modulation modes generate frequency,
phase, and/or amplitude data destined for the DDS signal
control parameters. In addition, the OSK function generates
amplitude data destined for the DDS. Each of these functions is
independently invoked using the appropriate control bit via the
serial I/O port.
The ability to activate each of these functions independently
makes it possible to have multiple data sources attempting to
drive the same DDS signal control parameter. To avoid contention,
the AD9910 has a built-in priority system. Table 5 summarizes
the priority for each of the DDS signal control parameters. The
rows of Table 5 list data sources for a particular DDS signal con-
trol parameter in descending order of precedence. For example,
if both the RAM and the parallel port are enabled and both are
programmed for frequency as the destination, then the DDS
frequency parameter is driven by the RAM and not the parallel
data port.
Table 5. Data Source Priority
Priority
DDS Signal Control Parameters
Frequency
Phase
Amplitude
Data Source
Conditions
Data Source
Conditions
Data Source
Conditions
Highest
Priority
RAM
RAM enabled and
data destination is
frequency
RAM
RAM enabled and
data destination is
phase or polar
OSK generator
OSK enabled (auto
mode)
DRG
DRG enabled and
data destination is
frequency
DRG
DRG enabled and
data destination is
phase
ASF register
OSK enabled
(manual mode)
Parallel data
port and FTW
register
Parallel data port
enabled and data
destination is
frequency
Parallel data port
enabled and data
destination is
phase
RAM
RAM enabled and
data destination is
amplitude or polar
FTW register
RAM enabled and
data destination is
phase, amplitude,
or polar
Parallel data port
concatenated with
the POW register
LSBs
Parallel data port
enabled and data
destination is polar
DRG
DRG enabled and
data destination is
amplitude
FTW in active
single tone
profile register
DRG enabled and
data destination is
phase or amplitude
POW register
RAM enabled and
destination is
frequency or
amplitude
Parallel data port
enabled and data
destination is
amplitude
FTW in active
single tone
profile register
Parallel data port
enabled and data
destination is
phase, amplitude,
or polar
POW in active
single tone profile
register
DRG enabled and
data destination is
frequency or
amplitude
Parallel data port
concatenated with
the ASF register
LSBs
Parallel data port
enabled and data
destination is
polar
FTW in active
single tone
profile register
None
POW in active
single tone profile
register
Parallel data port
enabled and data
destination is
frequency or
amplitude
ASF in active single
tone profile
register
Enable amplitude
scale from single
tone profiles bit
(CFR2[24]) set
Lowest
Priority
POW in active
single tone profile
register
None
No amplitude
scaling
None
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