參數(shù)資料
型號(hào)： AD9910BSVZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 31/64頁
文件大?。?/td> 0K
描述： IC DDS 1GSPS 14BIT PAR 100TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
標(biāo)準(zhǔn)包裝： 1,000
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
Data Sheet
AD9910
Rev. D | Page 37 of 64
RAM_SWP_OVER
WAVEFORM START ADDRESS 0
WAVEFORM END ADDRESS 0
1
WAVEFORM START ADDRESS 1
WAVEFORM END ADDRESS 1
1
WAVEFORM END ADDRESS 2
1
RAM PROFILE
0
1
2
WAVEFORM START ADDRESS 2
RAM
ADDRESS
I/O_UPDATE
Δt0
Δt1
Δt2
1
2
3
4
5
6
7
06479-
025
Figure 44. Internal Profile Control Timing Diagram (Burst)
The gray bar across the top indicates the time interval over
which the designated profile is in effect. The circled numbers
indicate specific events as follows:
Event 1—An I/O update registers the internal profile control bits
(in Control Function Register 1) as 0010. The RAM_SWP_OVR
pin is set to Logic 0. The state machine is initialized to the
waveform start address of RAM Profile 0 and begins increment-
ing through the address range for RAM Profile 0 at intervals of
Δt0 (as specified by the address step rate for RAM Profile 0).
Event 2—The state machine reaches the waveform end address
of RAM Profile 0, and the RAM_SWP_OVR pin generates a
positive pulse spanning two DDS clock cycles.
Event 3—Having reached the waveform end address of RAM
Profile 0, the next expiration of the internal timer causes the
state machine to advance to RAM Profile 1. The state machine
is initialized to the waveform start address of RAM Profile 1
and begins incrementing through the address range for RAM
Profile 1 at intervals of Δt1.
Event 4—The state machine reaches the waveform end address
of RAM Profile 1, and the RAM_SWP_OVR pin generates a
positive pulse spanning two DDS clock cycles.
Event 5—Having reached the waveform end address of RAM
Profile 1, the next expiration of the internal timer causes the
state machine to advance to RAM Profile 2. The state machine
initializes to the waveform start address of RAM Profile 2 and
begins incrementing through the address range for RAM
Profile 2 at intervals of Δt2.
Event 6—The state machine reaches the waveform end address of
RAM Profile 2, and the RAM_SWP_OVR pin generates a positive
pulse spanning two DDS clock cycles.
Event 7—Having reached the waveform end address of RAM
Profile 2, the next expiration of the internal timer causes the
state machine to halt and marks completion of the burst
waveform generation process.
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