參數(shù)資料
型號(hào)： AD9910BSVZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 53/64頁(yè)
文件大小： 0K
描述： IC DDS 1GSPS 14BIT PAR 100TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
標(biāo)準(zhǔn)包裝： 1,000
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
Data Sheet
AD9910
Rev. D | Page 57 of 64
Control Function Register 2 (CFR2)—Address 0x01
Four bytes are assigned to this register.
Table 19. Bit Descriptions for CFR2
Bit(s)
Mnemonic
Description
31:25
Open
24
Enable amplitude scale
from single tone profiles
Ineffective if CFR2[19 ] = 1 or CFR1[31] = 1 or CFR1[9] = 1.
0 = the amplitude scaler is bypassed and shut down for power conservation (default).
1 = the amplitude is scaled by the ASF from the active profile.
23
Internal I/O update active
This bit is effective without the need for an I/O update.
0 = serial I/O programming is synchronized with the external assertion of the
I/O_UPDATE pin, which is configured as an input pin (default).
1 = serial I/O programming is synchronized with an internally generated I/O update
signal (the internally generated signal appears at the I/O_UPDATE pin, which is
configured as an output pin).
22
SYNC_CLK enable
0 = the SYNC_CLK pin is disabled; static Logic 0 output.
1 = the SYNC_CLK pin generates a clock signal at f
SYSCLK; used for synchronization of the
serial I/O port (default).
21:20
Digital ramp destination
See Table 11 for details. Default is 00b. See the Digital Ramp Generator (DRG) section for
details.
19
Digital ramp enable
0 = disables digital ramp generator functionality (default).
1 = enables digital ramp generator functionality.
18
Digital ramp no-dwell high
See the Digital Ramp Generator (DRG) section for details.
0 = disables no-dwell high functionality (default).
1 = enables no-dwell high functionality.
17
Digital ramp no-dwell low
See the Digital Ramp Generator (DRG) section for details.
0 = disables no-dwell low functionality (default).
1 = enables no-dwell low functionality.
16
Read effective FTW
0 = a serial I/O port read operation of the FTW register reports the contents of the FTW
register (default).
1 = a serial I/O port read operation of the FTW register reports the actual 32-bit word
appearing at the input to the DDS phase accumulator.
15:14
I/O update rate control
Ineffective unless CFR2[23] = 1. Sets the prescale ratio of the divider that clocks the auto I/O
update timer as follows:
00 = divide-by-1 (default).
01 = divide-by-2.
10 = divide-by-4.
11 = divide-by-8.
13:12
Open
11
PDCLK enable
0 = the PDCLK pin is disabled and forced to a static Logic 0 state; the internal clock signal
continues to operate and provide timing to the data assembler.
1 = the internal PDCLK signal appears at the PDCLK pin (default).
10
PDCLK invert
0 = normal PDCLK polarity; Q-data associated with Logic 1, I-data with Logic 0 (default).
1 = inverted PDCLK polarity.
9
TxEnable invert
0 = no inversion.
1 = inversion.
8
Open
7
Matched latency enable
0 = simultaneous application of amplitude, phase, and frequency changes to the DDS
arrive at the output in the order listed (default).
1 = simultaneous application of amplitude, phase, and frequency changes to the DDS
arrive at the output simultaneously.
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