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| 型號： | AD9910BSVZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS 1GSPS 14BIT PAR 100TQFP |
| 產(chǎn)品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) |
| 標準包裝： | 1,000 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
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AD9910
Data Sheet
Rev. D | Page 24 of 64
Auxiliary DAC
An 8-bit auxiliary DAC controls the full-scale output current of
the main DAC (IOUT). An 8-bit code word stored in the appropriate
register map location sets IOUT according to the following equation:
+
=
96
1
4
.
86
CODE
R
I
SET
OUT
where RSET is the value of the RSET resistor (in ohms) and CODE
is the 8-bit value supplied to the auxiliary DAC (default is 127).
For example, with RSET = 10,000 Ω and CODE = 127, then IOUT =
20.07 mA.
INVERSE SINC FILTER
The sampled carrier data stream is the input to the digital-to-
analog converter (DAC) integrated into the AD9910. The
DAC output spectrum is shaped by the characteristic sin(x)/x
(or sinc) envelope, due to the intrinsic zero-order hold effect
associated with DAC generated signals. The sinc envelope
can be compensated for because its shape is well known. This
envelope restoration function is provided by the inverse sinc
filter preceding the DAC. The inverse sinc filter is implemented
as a digital FIR filter. It has a response characteristic that very
nearly matches the inverse of the sinc envelope. The response
of the inverse sinc filter is shown in Figure 28 (with the sinc
envelope for comparison).
The inverse sinc filter is enabled using CFR1[22]. The filter tap
coefficients are given in Table 6. The filter operates by distorting
the data prior to its arrival at the DAC in such a way as to
compensate for the sinc envelope that otherwise distorts the
spectrum.
When the inverse sinc filter is enabled, it introduces a ~3.0 dB
insertion loss. The inverse sinc compensation is effective for output
frequencies up to approximately 40% of the DAC sample rate.
Table 6. Inverse Sinc Filter Tap Coefficients
Tap No.
Tap Value
1, 7
35
2, 6
+134
3, 5
562
4
+6729
In Figure 28, the sinc envelope introduces a frequency dependent
attenuation that can be as much as 4 dB at the Nyquist frequency
( of the DAC sample rate). Without the inverse sinc filter, the
DAC output suffers from the frequency dependent droop of
the sinc envelope. The inverse sinc filter effectively flattens the
droop to within ±0.05 dB, as shown in Figure 29, which shows
the corrected sinc response with the inverse sinc filter enabled.
1
0
–1
–2
–3
–4
0
0.1
0.2
0.4
0.3
0.5
06479-
011
(d
B)
FREQUENCY RELATIVE TO DAC SAMPLE RATE
INVERSE
SINC
Figure 28. Sinc and Inverse Sinc Responses
–2.8
–2.9
–3.0
–3.1
0
0.1
0.2
0.4
0.3
0.5
06479-
012
(d
B)
FREQUENCY RELATIVE TO DAC SAMPLE RATE
COMPENSATED RESPONSE
Figure 29. DAC Response with Inverse Sinc Compensation
CLOCK INPUT (REF_CLK/REF_CLK)
REF_CLK/REF_CLK Overview
The AD9910 supports a number of options for producing the
internal SYSCLK signal (that is, the DAC sample clock) via the
REF_CLK/REF_CLK input pins. The REF_CLK input can be
driven directly from a differential or single-ended source, or it
can accept a crystal connected across the two input pins. There
is also an internal phase-locked loop (PLL) multiplier that can
be independently enabled. A block diagram of the REF_CLK
functionality is shown in Figure 30. The various input configu-
rations are controlled by the XTAL_SEL pin and the control bits
in the CFR3 register. Figure 30 also shows how the CFR3 control
bits are associated with specific functional blocks.
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