參數(shù)資料
型號: AD9910BSVZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 10/64頁
文件大小: 0K
描述: IC DDS 1GSPS 14BIT PAR 100TQFP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計資源: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
標準包裝: 1,000
分辨率(位): 14 b
主 fclk: 1GHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 帶卷 (TR)
AD9910
Data Sheet
Rev. D | Page 18 of 64
RAM MODULATION MODE
The RAM modulation mode (see Figure 23) is activated via the
RAM enable bit and assertion of the I/O_UPDATE pin (or a
profile change). In this mode, the modulated DDS signal control
parameters are supplied directly from RAM.
The RAM consists of 32-bit words and is 1024 words deep.
Coupled with a sophisticated internal state machine, the RAM
provides a very flexible method for generating arbitrary, time
dependent waveforms. A programmable timer controls the rate
at which words are extracted from the RAM for delivery to the
DDS. Thus, the programmable timer establishes a sample rate at
which 32-bit samples are supplied to the DDS.
The selection of the specific DDS signal control parameters that
serve as the destination for the RAM samples is also programmable
through eight independent RAM profile registers. Select a par-
ticular profile using the three external profile pins (PROFILE[2:0]).
A change in the state of the profile pins with the next rising
edge on SYNC_CLK activates the selected RAM profile.
In RAM modulation mode, the ability to generate a time depen-
dent amplitude, phase, or frequency signal enables modulation
of any one of the parameters controlling the DDS carrier signal.
Furthermore, a polar modulation format is available that partitions
each RAM sample into a magnitude and phase component; 16 bits
are allocated to phase and 14 bits are allocated to magnitude.
06479-
006
16
PARALLEL
INPUT
PDCLK
SCLK
SDIO
I/O_RESET
PROFILE[2:0]
I/O_UPDATE
RAM
E
X
T
_P
W
R_DW
N
DAC_RSET
IOUT
CS
TxENABLE
DAC FSC
OSK
A
θ
INVERSE
SINC
FILTER
CLOCK
AMPLITUDE (A)
FREQUENCY
(ω)
PHASE (θ)
DIGITAL
RAMP
GENERATOR
8
DAC FSC
8
2
MULTICHIP
SYNCHRONIZATION
SYSCLK
PLL
÷2
CL
O
CK
M
O
DE
REF_CLK
REFCLK_OUT
XTAL_SEL
PARALLEL DATA
TIMING AND
CONTROL
SER
IA
L
I/O
P
OR
T
2
AD9910
PROGRAMMING
REGISTERS
OUTPUT
SHIFT
KEYING
DATA
ROUTE
AND
PARTITION
CONTROL
3
INTERNAL CLOCK TIMING
AND CONTROL
ω
Acos (ωt + θ)
Asin (ωt + θ)
SYN
C
_
SMP_
ER
R
S
Y
NC_O
UT
S
Y
NC_I
N
P
LL_
LOC
K
P
LL_
LOOP
_
FI
L
T
ER
MA
ST
ER
_
R
ESET
2
DDS
AUX
DAC
8-BIT
DAC
14-BIT
RAM_SWP_OVR
DRCTL
DRHOLD
DROVER
S
Y
NC_CL
K
POWER-
DOWN
CONTROL
Figure 23. RAM Modulation Mode
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