參數(shù)資料
型號(hào): AD9895KBCZRL
廠商: Analog Devices Inc
文件頁數(shù): 6/58頁
文件大?。?/td> 0K
描述: IC CCD SIGNAL PROC/GEN 64-CSPBGA
標(biāo)準(zhǔn)包裝: 2,000
類型: CCD 信號(hào)處理器,12 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
安裝類型: 表面貼裝
封裝/外殼: 64-VFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 64-CSPBGA(9x9)
包裝: 帶卷 (TR)
REV. A
–14–
AD9891/AD9895
P[0]
PIXEL
PERIOD
RG
H1/H3
RGf[12]
P[48] = P[0]
Hf[24]
SHP[28]
CCD
SIGNAL
P[24]
P[12]
P[36]
Hr[0]
RGr[0]
SHD[48]
NOTES
ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.
DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.
POSITION
tS1
Figure 10. High Speed Clock Default and Programmable Locations
FIXED CROSSOVER VOLTAGE
H1/H3
H2/H4
t
PD
H2/H4
H1/H3
t
RISE
t
PD < tRISE
Figure 11. H-Clock Inverse Phase Relationship
NOTES
DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.
OUTPUT DELAY (
t
OD) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.
P[0]
P[48] = P[0]
PIXEL
PERIOD
P[12]
P[24]
P[36]
DOUT
DCLK
t
OD
Figure 12. Digital Output Phase Adjustment
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