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參數(shù)資料
| 型號： | AD9895KBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROC/GEN 64-CSPBGA |
| 標準包裝： | 2,000 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFBGA，CSPBGA |
| 供應商設(shè)備封裝： | 64-CSPBGA（9x9） |
| 包裝： | 帶卷 (TR) |
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REV. A
AD9891/AD9895
–11–
SYSTEM OVERVIEW
Figure 5 shows the typical system block diagram for the AD9891/
AD9895 used in Master Mode. The CCD output is processed by
the AD9891/AD9895’s AFE circuitry, which consists of a CDS,
PxGA, VGA, black level clamp, and an A/D converter. The digi-
tized pixel information is sent to the digital image processor chip,
which performs the post-processing and compression. To operate
the CCD, all CCD timing parameters are programmed into the
AD9891/AD9895 from the system microprocessor, through the
3-wire serial interface. From the system master clock, CLI, pro-
vided by the image processor or external crystal, the AD9891/
AD9895 generates all of the CCD’s horizontal and vertical clocks
and all internal AFE clocks. External synchronization is provided
by a SYNC pulse from the microprocessor, which will reset
internal counters and resync the VD and HD outputs.
CCDIN
MSHUT
STROBE
H1–H4, RG, VSUB
V1–V4, VSG1–VSG8, SUBCK
CCD
V-DRIVER
AD989x
DIGITAL
IMAGE
PROCESSING
ASIC
P
DOUT
DCLK
CLPOB/PBLK
LD/FD
HD, VD
CLI
SERIAL
INTERFACE
SYNC
Figure 5. Typical System Block Diagram, Master Mode
Alternatively, the AD9891/AD9895 may be operated in Slave
Mode, in which the VD and HD are provided externally from
the image processor. In this mode, all AD9891/AD9895 timing
will be synchronized with VD and HD.
The H-drivers for H1–H4 and RG are included in the AD9891/
AD9895, allowing these clocks to be directly connected to the CCD.
H-drive voltage of up to 5 V is supported. An external V-driver is
required for the vertical transfer clocks, the sensor gate pulses,
and the substrate clock.
The AD9891/AD9895 also includes programmable MSHUT
and STROBE outputs, which may be used to trigger mechani-
cal shutter and strobe (flash) circuitry.
Figure 6 shows the horizontal and vertical counter dimensions
for the AD9891/AD9895. All internal horizontal and vertical
clocking is programmed using these dimensions to specify line
and pixel locations.
12-BIT HORIZONTAL = 4096 PIXELS MAX
12-BIT VERTICAL = 4096 LINES MAX
MAXIMUM
FIELD
DIMENSIONS
Figure 6. Vertical and Horizontal Counters
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