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參數(shù)資料
| 型號： | AD9895KBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/58頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROC/GEN 64-CSPBGA |
| 標準包裝： | 2,000 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFBGA，CSPBGA |
| 供應商設備封裝： | 64-CSPBGA（9x9） |
| 包裝： | 帶卷 (TR) |
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REV. A
AD9891/AD9895
–25–
V1
V2
V1 USES SEQUENCE 0
V3
V4
HD
V2 USES SEQUENCE 0
V3 USES SEQUENCE 1
V4 USES SEQUENCE 1
V5
V6
V5 USES SEQUENCE 0
V7
V8
V6 USES SEQUENCE 0
V7 USES SEQUENCE 1
V8 USES SEQUENCE 1
ACTIVE
IMAGE
AREA
STORAGE
AREA
Figure 28. Example of Frame Transfer CCD Mode using V1–V8
The frame transfer CCD also requires additional timing control
when decimating the image for Preview Mode. The
AD9891/AD9895 contain registers to independently stop the
operation of the V5–V8 outputs while the V1–V4 outputs con-
tinue to run or to stop the V1–V4 outputs, while the V5–V8
outputs remain operational. The FREEZE and RESUME Regis-
ters specify the pixel locations within each line of a region where
the V1–V4 or V5–V8 clock outputs will start to hold their state,
and where they will resume normal operation. FREEZE and
RESUME can be used in any region during the frame readout.
Vertical Sensor Gate (Shift Gate) Timing
With an interline CCD, the vertical sensor gates (VSG) are used to
transfer the pixel charges from the light-sensitive image area into the
light-shielded vertical registers. When a mechanical shutter is not being
used, this transfer will effectively end the exposure period during the
image acquisition. From the light-shield vertical registers, the image
is then read out line-by-line by using the vertical transfer pulses
V1–V4 in conjunction with the high speed horizontal clocks.
VD
HD
PROGRAMMABLE SETTINGS FOR EACH SEQUENCE:
1: START POLARITY OF PULSE
3: 2ND TOGGLE POSITION
2: 1ST TOGGLE POSITION
4: ACTIVE LINE FOR VSG PULSE WITHIN THE FIELD
VSG1–VSG8
4
12
3
Figure 29. Vertical Sensor Gate Pulse Placement
Table XIII. Sensor Gate Register Parameters
Register
Length
Range
Description
SGPOL
1b
High/Low
Sensor Gate Starting Polarity for Sequence 0–3
SGTOG1
12b
0–4095 Pixel Location
First Toggle Position for Sequence 0–11
SGTOG2
12b
0–4095 Pixel Location
Second Toggle Position for Sequence 0–11
SGACTLINE
12b
0–4095 Pixel Location
Line in Field where VSG1–VSG8 Are Active
SGSEL
2b
Sequence 0–3
Selects Sequence 0–3 for VSG1–VSG8
SGMASK
8b
8 Individual Bits
Masking for any of VSG1–VSG8 Signals (0 = On, 1 = Mask)
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