參數(shù)資料
型號(hào)： AD9895KBCZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 29/58頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROC/GEN 64-CSPBGA
標(biāo)準(zhǔn)包裝： 2,000
類型： CCD 信號(hào)處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
安裝類型： 表面貼裝
封裝/外殼： 64-VFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 64-CSPBGA（9x9）
包裝： 帶卷 (TR)
REV. A
AD9891/AD9895
–35–
VD
HD
NOTES
1. SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO ZERO.
2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR x025).
3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR x026).
4. IF SYNCSUSPEND = 1, VERTICAL CLOCKS AND H1–H2, RG ARE HELD AT THEIR DEFAULT POLARITIES.
5. IF SYNCSUSPEND = 0, THEN ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL SYNC RESET EDGE.
SUSPEND
SYNC
H124, RG, V1–V4,
VSG, SUBCK
Figure 43. SYNC Timing to Synchronize AD989x with External Timing
VD
NOTES
1. INTERNAL H-COUNTER IS RESET 8 CLOCK CYCLES AFTER THE HD FALLING EDGE.
2. PxGA STEERING IS SYNCHRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN).
HD
XX
000
1
2
XX
111
0
3
XX
X1
1
00
X
PxGA GAIN
REGISTER
CLI
0123
4
5
6
7
89
10
11
12
13
14
01
2
3
02
3
XX
X
H-COUNTER
(PIXEL COUNTER)
3ns MIN
4
H-COUNTER
RESET
Figure 44. External VD/HD and Internal H-Counter Synchronization, SLAVE Mode
POWER-DOWN MODE OPERATION
The AD9891/AD9895 contain three different power-down
modes to optimize the overall power dissipation in a particular
application. Bits [1:0] of the OPRMODE Register control the
power-down state of the device:
OPR_MODE [1:0] = 00 = Normal Operation (full power)
OPR_MODE[1:0] = 01 = Power-Down 1 Mode
OPR_MODE[1:0] = 10 = Power-Down 2 Mode
OPR_MODE[1:0] = 11 = Power-Down 3 Mode (lowest
overall power)
Table XVI summarizes the operation of each power-down mode.
Note that in any mode, the OUT_CONT Register takes priority
over the power-down modes where the digital output states are
concerned. Power-Down 3 Mode has the lowest power consump-
tion, and it even powers down the crystal oscillator circuit
between CLI and CLO. Thus, if CLI and CLO are being used
with a crystal to generate the master clock, this circuit will be
powered down and there will be no clock signal. When returning
from Power-Down 3 Mode to normal operation, the timing core
must be reset at least 500 ms after the OPR_MODE Register is
written to. This will allow sufficient time for the crystal circuit
to settle.
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