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參數(shù)資料
| 型號(hào)： | AD9895KBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROC/GEN 64-CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | CCD 信號(hào)處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 64-CSPBGA（9x9） |
| 包裝： | 帶卷 (TR) |
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REV. A
AD9891/AD9895
–31–
RR
Gb
Gr
BB
CCD: PROGRESSIVE BAYER
LINE0
GAIN0, GAIN1, GAIN0, GAIN1, ...
RR
Gr
Gb
BB
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3, ...
GAIN0, GAIN1, GAIN0, GAIN1, ...
MOSAIC SEPARATE COLOR
STEERING MODE
Figure 38a. CCD Color Filter Example: Progressive Scan
LINE0
GAIN0, GAIN1, GAIN0, GAIN1, ...
RR
Gr
LINE1
LINE2
GAIN0, GAIN1, GAIN0, GAIN1, ...
Gb
BB
LINE0
GAIN2, GAIN3, GAIN2, GAIN3, ...
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3, ...
MOSAIC INTERLACED
COLOR STEERING MODE
Gb
BB
Gb
BB
Gb
BB
RR
Gr
RR
Gr
RR
Gr
EVEN FIELD
ODD FIELD
CCD: INTERLACED BAYER
Figure 38b. CCD Color Filter Example: Interlaced
VD
NOTES
1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “0101” LINE.
2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN “0101” AND “2323” LINES.
3. FLD STATUS IS IGNORED.
HD
00
0
11
22
33
22
33
X
PxGA GAIN
REGISTER
FLD
ODD FIELD
EVEN FIELD
Figure 39a. Mosaic Separate Color Steering Mode
VD
NOTES
1. FLD FALLING EDGE (START OF ODD FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO “0101” LINE.
2. FLD RISING EDGE (START OF EVEN FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO “2323” LINE.
3. HD FALLING EDGES WILL RESET THE PxGA GAIN REGISTER STEERING TO EITHER “0” (FLD = ODD) OR “2” (FLD = EVEN).
HD
00
22
2
0
2
11
33
00
11
22
33
X
PxGA GAIN
REGISTER
FLD
ODD FIELD
EVEN FIELD
Figure 39b. Mosaic Interlaced Color Steering Mode
example, the Mosaic Separate Steering Mode accommodates the
popular “Bayer” arrangement of Red, Green, and Blue filters
(see Figure 38a).
The same Bayer pattern can also be interlaced, and the Mosaic
Interlaced Mode should be used with this type of CCD (see
Figure 38b). The color steering performs the proper multiplex-
ing of the R, G, and B gain values (loaded into the PxGA gain
registers) and is synchronized by the vertical (VD) and horizon-
tal (HD) sync pulses. The PxGA gain for each of the four
channels is variable from –2dB to +10 dB, controlled in 64
steps through the serial interface. The PxGA gain curve is
shown in Figure 40.
COLOR
STEERING
CONTROL
4:1
MUX
3
PxGA
STEERING
MODE
SELECTION
2
6
VD
HD
PxGA GAIN
REGISTERS
CONTROL
REGISTER
BITS D0:D2
SHP/SHD
VGA
CDS
GAIN0
GAIN1
GAIN2
GAIN3
PxGA
Figure 37. PxGA Block Diagram
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