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參數(shù)資料
| 型號： | AD9824KCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/24頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROC 14BIT 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
REV. 0
AD9824
–15–
SDATA
SCK
SL
A0 A1
A2
D0
D10 D0
D9
D0
D7
RNW
0
D9
0
00
D0
1
217
35
34
27
26
16
6
5
4
3
44
45
51
63
62
57
56
50
68
...
10 BITS
ACG GAIN
D5
D0
D5
D0
D5
...
NOTES
1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING ONE ADDRESS AT A TIME.
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.
3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.
8 BITS
CLAMP LEVEL
10 BITS
CONTROL
11 BITS
OPERATION
6 BITS
PxGA GAIN0
6 BITS
PxGA GAIN1
6 BITS
PxGA GAIN2
6 BITS
PxGA GAIN3
Figure 23. Continuous Serial Write Operation to All Registers
SDATA
A0
A1
A2
D1
D0
D1
D2
D3
D4
D5
D0
D3
D2
D4
0
23
24
12
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
29
18
...
D5
0
01
D5
D0
RNW
SCK
SL
PxGA GAIN0
PxGA GAIN1
PxGA GAIN3
PxGA GAIN2
...
Figure 24. Continuous Serial Write Operation to All PxGA Gain Registers
Table II. Operation Register Contents (Default Value x000)
Optical Black Clamp
Reset
Power-Down Modes
Channel Selection
D10
D9
D8
D7
D6
D5
D4
D3 D2
D1 D0
0
1
0
1
0
1
2
0
1
0
Enable Clamping
0 Normal
0
0 Normal Power
0
CCD Mode
1
Disable Clamping
1 Reset All Registers
0
1 Test Only
0
1
AUX1 Mode
to Default
1
0 Standby
1
0
AUX2 Mode
11 Total Power-Down
11
Test Only
NOTES
1Must be set to zero.
2Set to one.
Table III. VGA Gain Register Contents (Default Value x000)
MSB
LSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Gain (dB)
X0
0
010111112.0
11
11111110
35.965
11
11111111
36.0
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