參數(shù)資料
型號: AD9824KCPZRL
廠商: Analog Devices Inc
文件頁數(shù): 10/24頁
文件大?。?/td> 0K
描述: IC CCD SIGNAL PROC 14BIT 48LFCSP
標(biāo)準(zhǔn)包裝: 2,500
類型: CCD 信號處理器,14 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
REV. 0
AD9824
–18–
RR
Gb
Gr
BB
CCD: PROGRESSIVE BAYER
LINE0
GAIN0, GAIN1, GAIN0, GAIN1...
RR
Gr
Gb
BB
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3...
GAIN0, GAIN1, GAIN0, GAIN1...
MOSAIC SEPARATE COLOR
STEERING MODE
Figure 26. CCD Color Filter Example: Progressive Scan
LINE0
GAIN0, GAIN1, GAIN0, GAIN1...
RR
Gr
LINE1
LINE2
GAIN0, GAIN1, GAIN0, GAIN1...
Gb
BB
LINE0
GAIN2, GAIN3, GAIN2, GAIN3...
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3...
CCD: INTERLACED BAYER
EVEN FIELD
VD SELECTED COLOR
STEERING MODE
ODD FIELD
Gb
BB
Gb
BB
Gb
BB
RR
Gr
RR
Gr
RR
Gr
Figure 27. CCD Color Filter Example: Interlaced
The same Bayer pattern can also be interlaced, and the VD
selected mode should be used with this type of CCD (see
Figure 27). The color steering performs the proper multiplexing
of the R, G, and B gain values (loaded into the PxGA gain regis-
ters) and is synchronized by the user with vertical (VD) and
horizontal (HD) sync pulses. For more detailed information, see
the PxGA Timing section. The PxGA gain for each of the four
channels is variable from –2.5 dB to +9.5 dB, controlled in 64
steps through the serial interface. The PxGA gain curve is
shown in Figure 28.
PxGA GAIN REGISTER CODE
10
32
PxGA
GAIN
dB
40
48
58
0
8
16
24
31
6
4
2
0
–2
–4
8
(100000)
(011111)
Figure 28. PxGA Gain Curve
Variable Gain Amplier
The VGA stage provides a gain range of 2 dB to 36 dB, program-
mable with 10-bit resolution through the serial digital interface.
Combined with approximately 4 dB from the PxGA stage, the
total gain range for the AD9824 is 6 dB to 40 dB. The minimum
gain of 6 dB is needed to match -a 1 V input signal with the
ADC full-scale range of 2 V. When compared to 1 V full-scale
systems (such as ADI’s AD9803), the equivalent gain range is
0 dB to 34 dB.
The VGA gain curve follows a “l(fā)inear-in-dB” shape. The exact
VGA gain can be calculated for any gain register value by using
the following equation:
Code Range
Gain Equation (dB)
0–1023
Gain = (0.0353)(Code)
As shown in the CCD Mode Specications, only the VGA gain
range from 2 dB to 36 dB has tested and guaranteed accuracy.
This corresponds to a VGA gain code range of 77 to 1023. The
Gain Accuracy Specications also include a PxGA gain of approxi-
mately 3.3 dB, for a total gain range of 6 dB to 40 dB.
VGA GAIN REGISTER CODE
36
0
VGA
GAIN
dB
127
255
383
511
639
767
895
1023
30
24
18
12
6
0
Figure 29. VGA Gain Curve (Gain from PxGA Not Included)
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a xed
black level reference, selected by the user in the clamp level
register. The clamp level is adjustable from 0 to 1020 LSB, in
256 steps. The resulting error signal is ltered to reduce noise,
and the correction value is applied to the ADC input through a
D/A converter. Normally, the optical black clamp loop is turned
on once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital clamping
is used during the post processing, the AD9824 optical black
clamping may be disabled using Bit D5 in the Operation Register
(see Serial Interface Timing and Internal Register Description
section). When the loop is disabled, the clamp level register may
still be used to provide programmable offset adjustment.
Horizontal timing is shown in Figure 6. The CLPOB pulse
should be placed during the CCD’s optical black pixels. It is
recommended that the CLPOB pulse duration be at least 20
pixels wide to minimize clamp noise. Shorter pulsewidths may be
used, but clamp noise may increase and the ability to track
low frequency variations in the black level will be reduced.
相關(guān)PDF資料
PDF描述
AD9826KRSZRL IC IMAGE SGNL PROC 16BIT 28-SSOP
AD9830ASTZ-REEL IC DDS 10BIT 50MHZ CMOS 48TQFP
AD9832BRU-REEL IC DDS 10BIT 25MHZ CMOS 16-TSSOP
AD9833BRM IC WAVEFORM GEN PROG 10-MSOP
AD9834BRU IC DDS W/COMP 2.3V 50MHZ 20TSSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9826 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 16-Bit Imaging Signal Processor
AD9826_12 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 16-Bit Imaging Signal Processor
AD9826-EB 制造商:Analog Devices 功能描述:- Bulk
AD9826KRS 制造商:Analog Devices 功能描述:AFE Video 1ADC 16-Bit 5V 28-Pin SSOP Tube 制造商:Analog Devices 功能描述:IC 16-BIT SIGNAL PROCESSOR
AD9826KRSRL 制造商:Analog Devices 功能描述:AFE Video 1ADC 16-Bit 5V 28-Pin SSOP T/R