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參數(shù)資料
| 型號： | AD9824KCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROC 14BIT 48LFCSP |
| 標準包裝： | 2,500 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
REV. 0
AD9824
–5–
ABSOLUTE MAXIMUM RATINGS
With
Respect
Parameter
To
Min Max
Unit
AVDD1, AVDD2
AVSS
–0.3 +3.9
V
DVDD1, DVDD2
DVSS
–0.3 +3.9
V
DRVDD
DRVSS
–0.3 +3.9
V
Digital Outputs
DRVSS
–0.3 DRVDD + 0.3 V
SHP, SHD, DATACLK
DVSS
–0.3 DVDD + 0.3
V
CLPOB, CLPDM, PBLK
DVSS
–0.3 DVDD + 0.3
V
SCK, SL, SDATA
DVSS
–0.3 DVDD + 0.3
V
VRT, VRB, CMLEVEL
AVSS
–0.3 AVDD + 0.3
V
BYP1-3, CCDIN
AVSS
–0.3 AVDD + 0.3
V
Junction Temperature
150
°C
Lead Temperature (10 sec)
300
°C
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period
tCP
33
ns
DATACLK High/Low Pulsewidth
tADC
13
16.7
ns
SHP Pulsewidth
tSHP
5
8.3
ns
SHD Pulsewidth
tSHD
5
8.3
ns
CLPDM Pulsewidth
tCDM
410
Pixels
CLPOB Pulsewidth*
tCOB
220
Pixels
SHP Rising Edge to SHD Falling Edge
tS1
0
8.3
ns
SHP Rising Edge to SHD Rising Edge
tS2
15
16.7
ns
Internal Clock Delay
tID
3.0
ns
Inhibited Clock Period
tINH
10
ns
DATA OUTPUTS
Output Delay
tOD
13
16
ns
Output Hold Time
tH
7.0
7.6
ns
Pipeline Delay
9
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
fSCLK
10
MHz
SL to SCK Setup Time
tLS
10
ns
SCK to SL Hold Time
tLH
10
ns
SDATA Valid to SCK Rising Edge Setup
tDS
10
ns
SCK Falling Edge to SDATA Valid Hold
tDH
10
ns
SCK Falling Edge to SDATA Valid Read
tDV
10
ns
*Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9824 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
(CL = 20 pF, fSAMP = 30 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7,
Serial Timing in Figures 21–24.)
ORDERING GUIDE
Temperature
Package
Model
Range
Description
Option
AD9824KCP
–20
°C to +85°C LFCSP
CP-48
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LFCSP Package
θ
JA = 26
°C/W*
*
θ
JA is measured using a 4-layer PCB with the exposed paddle
soldered to the board.
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